Datasheet
0
0
Drain Current
0
t1
0
0
t2
t3
a) Current Limit Only
V
SYS
V
DS
I
LIM
I
P
V
GATE
V
GSL
V
TH
t
ON
Source Voltage-toGate-
b) Power Limit and Current Limit
V
DS
Drain Current
t
ON
0
V
SYS
I
LIM
V
GATE
V
GSL
V
TH
t
ON
=
C
L
x V
SYS
2
2 x P
MOSFET(LIM)
C
L
x P
MOSFET(LIM)
2 x I
LIM
2
+
LM25066I/A
VIN
GND
PGD
OUT
Q1
GND
SENSE
R
S
R
L
C
L
V
SYS
LM25066I/A
VIN
GND
PGD
OUT
Q1
C
L
R
L
GND
SENSE
R
S
V
SYS
LM25066I, LM25066IA
SNVS824C –JUNE 2012–REVISED MARCH 2013
www.ti.com
Figure 38. A. No Load Current During Turn-On
Load Draws Current During Turn-On
Figure 39. Current During Turn-On
B) Turn-On with Power Limit and Current Limit: The maximum allowed power dissipation in Q
1
(P
MOSFET(LIM)
)
is defined by the resistor at the PWR pin, and the current sense resistor R
S
. See POWER LIMIT THRESHOLD. If
the current limit threshold (I
LIM
) is higher than the current defined by the power limit threshold at maximum V
DS
(P
MOSFET(LIM)
/V
SYS
), the circuit operates initially in the power limit mode when the V
DS
of Q
1
is high and then
transitions to current limit mode as the current increases to I
LIM
and V
DS
decreases. Assuming the load (R
L
) is not
connected during turn-on, the time for the output voltage to reach its final value is approximately equal to:
(6)
For example, if V
SYS
= 12V, C
L
= 1000 µF, I
LIM
= 1A, and P
MOSFET(LIM)
= 10W, t
ON
calculates to ≊12.2 ms, and the
initial current level (I
P
) is approximately 0.83A. The Fault Timeout Period must be set longer than t
ON
.
Figure 40. MOSFET Power Up Waveforms
TIMER CAPACITOR, C
T
The TIMER pin capacitor (C
T
) sets the timing for the insertion time delay, fault timeout period, and the restart
timing of the LM25066I/A.
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