Datasheet

LM25066I, LM25066IA
SNVS824C –JUNE 2012–REVISED MARCH 2013 www.ti.com
The SMBus address of the LM25066I/A is captured based on the states of the ADR0, ADR1, and ADR2 pins
(GND, NC, VDD) during turn-on and is latched into a volatile register once VDD has exceeded its POR threshold
of 2.6V. Reassigning or postponing the address capture is accomplished by holding the VREF pin to ground.
Pulling the VREF pin low will also reset the logic and erase the volatile memory of the LM25066I/A. Once
released, the VREF pin will charge up to its final value and the address will be latched into a volatile register
once the voltage at the VREF exceeds 2.4V.
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