Datasheet

1V
1 2 3 7 8
2 mA pulldown
90 PA
Fault
Detection
GATE
Pin
Loa
d
Current
T
I
LIMI
Pin
TIME
R
0.3V
t
RESTART
1.
7
V
Fault Timeout
Period
22 PA
Gate Charge
2.8
PA
LM25066I/A
Restart
Control
VIN
V
SYS
UVLO/EN
OVLO
GND
R1
R2
R3
LM25066I, LM25066IA
www.ti.com SNVS824C –JUNE 2012–REVISED MARCH 2013
active as described in Fault Timer and Restart. If the power limit condition persists for longer than the Fault
Timeout Period set by the timer capacitor, C
T
, the IIN_OC_FAULT bit in the STATUS_INPUT (7Ch) register, the
INPUT bit in the STATUS_WORD (79h) register, and the IIN_OC/PFET_OP_FAULT bit in the
DIAGNOSTIC_WORD (E1h) register will be toggled high and SMBA pin will be pulled low unless this feature is
disabled using the ALERT_MASK (D8h) register.
Fault Timer and Restart
When the current limit or power limit threshold is reached during turn-on, or as a result of a fault condition, the
gate-to-source voltage of Q
1
is controlled to regulate the load current and power dissipation in Q
1
. When either
limiting function is active, a 90 µA fault timer current source charges the external capacitor (C
T
) at the TIMER pin
as shown in Figure 32 (Fault Timeout Period). If the fault condition subsides during the Fault Timeout Period
before the TIMER pin reaches 1.7V, the LM25066I/A returns to the normal operating mode and C
T
is discharged
by the 1.9 mA current sink. If the TIMER pin reaches 1.7V during the Fault Timeout Period, Q
1
is switched off by
a 2 mA pulldown current at the GATE pin. The subsequent restart procedure then depends on the selected retry
configuration.
If the RETRY pin is high, the LM25066I/A latches the GATE pin low at the end of the Fault Timeout Period. C
T
is
then discharged to ground by the 2.8 µA fault current sink. The GATE pin is held low by the 2 mA pulldown
current until a power up sequence is externally initiated by cycling the input voltage (V
SYS
), or momentarily pulling
the UVLO/EN pin below its threshold with an open-collector or open-drain device as shown in Figure 33. The
voltage at the TIMER pin must be <0.3V for the restart procedure to be effective. The TIMER_LATCHED_OFF
bit in the DIAGNOSTIC_WORD (E1h) register will remain high while the latched off condition persists.
Figure 33. Latched Fault Restart Control
The LM25066I/A provides an automatic restart sequence which consists of the TIMER pin cycling between 1.7V
and 1V seven times after the Fault Timeout Period, as shown in Figure 34. The period of each cycle is
determined by the 90 µA charging current, and the 2.8 µA discharge current, and the value of the capacitor C
T
.
When the TIMER pin reaches 0.3V during the eighth high-to-low ramp, the 22 µA current source at the GATE pin
turns on Q
1
. If the fault condition is still present, the Fault Timeout Period and the restart sequence repeat. The
RETRY pin allows selecting no retries or infinite retries. Finer control of the retry behavior can be achieved
through the DEVICE_SETUP (D9h) register. Retry counts of 0, 1, 2, 4, 8, 16 or infinite may be selected by
setting the appropriate bits in the DEVICE_SETUP (D9h) register.
Figure 34. Restart Sequence
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