Datasheet

LM25066I, LM25066IA
SNVS824C –JUNE 2012–REVISED MARCH 2013 www.ti.com
Gate Control
A charge pump provides the voltage at the GATE pin to enhance the N-Channel MOSFET’s gate. During normal
operating conditions (t
3
in )Figure 32) the gate of Q
1
is held charged by an internal 22 µA current source. The
voltage at the GATE pin (with respect to ground) is limited by an internal 18.8 V zener diode. See the graph
“GATE Pin Voltage” shown previously. Since the gate-to-source voltage applied to Q
1
could be as high as 18.8 V
during various conditions, a zener diode with the appropriate voltage rating must be added between the GATE
and OUT pins if the maximum V
GS
rating of the selected MOSFET is less than 18.8 V. The external zener diode
must have a forward current rating of at least 190 mA. When the system voltage is initially applied, the GATE pin
is held low by a 190 mA pulldown current. This helps prevent an inadvertent turn-on of the MOSFET through its
drain-gate capacitance as the applied system voltage increases.
During the insertion time (t
1
in Figure 32) the GATE pin is held low by a 2 mA pulldown current. This maintains
Q
1
in the off-state until the end of t
1
, regardless of the voltage at VIN or UVLO. Following the insertion time (t
2
in
Figure 32), the gate voltage of Q
1
is controlled to keep the current or power dissipation level from exceeding the
programmed levels. While in the current or power limiting mode, the TIMER pin capacitor is charging. If the
current and power limiting cease before the TIMER pin reaches 1.7V, the TIMER pin capacitor then discharges,
and the circuit begins normal operation. If the inrush limiting condition persists such that the TIMER pin reached
1.7V during t
2
, the GATE pin is then pulled low by the 190 mA pulldown current. The GATE pin is then held low
until either a power up sequence is initiated (RETRY pin to VDD), or an automatic retry is attempted (RETRY pin
to GROUND). See Fault Timer and Restart. If the system input voltage falls below the UVLO threshold or rises
above the OVLO threshold, the GATE pin is pulled low by the 2 mA pulldown current to switch off Q
1
.
Current Limit
The current limit threshold is reached when the voltage across the sense resistor R
S
(VIN to SENSE) exceeds
the internal voltage limit of 25 mV or 46 mV depending on whether the CL pin is connected to GND or VDD,
respectively. In the current limiting condition, the GATE voltage is controlled to limit the current in MOSFET Q
1
.
While the current limit circuit is active, the fault timer is active as described in Fault Timer and Restart. If the load
current falls below the current limit threshold before the end of the Fault Timeout Period, the LM25066I/A
resumes normal operation. If the current limit condition persists for longer than the Fault Timeout Period set by
the timer capacitor, C
T
, the IIN OC FAULT bit in the STATUS_INPUT (7Ch) register, the INPUT bit in the
STATUS_WORD (79h) register, and the IIN_OC/PFET_OP_FAULT bit in the DIAGNOSTIC_WORD (E1h)
register will be toggled high and SMBA pin will be pulled low unless this feature is disabled using the
ALERT_MASK (D8h) register. For proper operation, the R
S
resistor value should be less than 200 mΩ. Higher
values may create instability in the current limit control loop. The current limit threshold pin value may be
overridden by setting appropriate bits in the DEVICE_SETUP register (D9h).
Circuit Breaker
If the load current increases rapidly (e.g. the load is short circuited), the current in the sense resistor (R
S
) may
exceed the current limit threshold before the current limit control loop is able to respond. If the current exceeds
1.8 or 3.6 times (user settable) the current limit threshold, Q
1
is quickly switched off by the 190 mA pulldown
current at the GATE pin, and a Fault Timeout Period begins. When the voltage across R
S
falls below the
threshold the 190 mA pulldown current at the GATE pin is switched off and the gate voltage of Q
1
is then
determined by the current limit or power limit functions. If the TIMER pin reaches 1.7V before the current limiting
or power limiting condition ceases, Q
1
is switched off by the 2 mA pulldown current at the GATE pin as described
in Fault Timer and Restart. A circuit breaker event will cause the CIRCUIT BREAKER FAULT bit in the
STATUS_MFR_SPECIFIC (80h) and DIAGNOSTIC_WORD (E1h) registers to be toggled high and SMBA pin will
be pulled low unless this feature is disabled using the ALERT_MASK (D8h) register. The circuit breaker pin
configuration may be overridden by setting appropriate bits in the DEVICE_SETUP (D9h) register.
Power Limit
An important feature of the LM25066I/A is the MOSFET power limiting. The Power Limit function can be used to
maintain the maximum power dissipation of MOSFET Q
1
within the device SOA rating. The LM25066I/A
determines the power dissipation in Q
1
by monitoring its drain-source voltage (SENSE to OUT), and the drain
current through R
S
(VIN to SENSE). The product of the current and voltage is compared to the power limit
threshold programmed by the resistor at the PWR pin. If the power dissipation reaches the limiting threshold, the
GATE voltage is controlled to regulate the current in Q
1
. While the power limiting circuit is active, the fault timer is
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