Datasheet
t
1
t
2
t
3
Normal Operation
Insertion Time
22 PA source
2.8
PA
90PA
I
LIMI
T
190 mA
pull-down
GATE
Pin
R
TIME
Pin
V
IN
V
SY
S
UVLO
POR
Loa
d
Current
Output
Voltag
e
(
OUT
Pin
)
PGD
In
rush
Limiting
1.7V
5.5 PA
2 mA pull
-down
LM25066I, LM25066IA
www.ti.com
SNVS824C –JUNE 2012–REVISED MARCH 2013
voltage reaches 1.7V. C
T
is then quickly discharged by an internal 1.9 mA pulldown current. The GATE pin then
switches on Q
1
when V
SYS
, the input supply voltage, exceeds the UVLO threshold. If V
SYS
is above the UVLO
threshold at the end of the insertion time, Q
1
switches on at that time. The GATE pin charge pump sources 22
µA to charge the gate capacitance of Q
1
. The maximum voltage at the GATE pin with respect to ground is limited
by an internal 18.8V zener diode.
As the voltage at the OUT pin increases, the LM25066I/A monitors the drain current and power dissipation of
MOSFET Q
1
. Inrush current limiting and/or power limiting circuits actively control the current delivered to the
load. During the inrush limiting interval (t
2
in Figure 32), an internal 90 µA fault timer current source charges C
T
.
If Q
1
’s power dissipation and the input current reduce below their respective limiting thresholds before the TIMER
pin reaches 1.7V, the 90 µA current source is switched off and C
T
is discharged by the internal 2.8 µA current
sink (t
3
in Figure 32). The PGD pin switches high when FB exceeds its rising threshold of 1.167V.
If the TIMER pin voltage reaches 1.7V before inrush current limiting or power limiting ceases during t
2
, a fault is
declared and Q
1
is turned off. See Fault Timer and Restart for a complete description of the fault mode.
The LM25066I/A will pull the SMBA pin low after the input voltage has exceeded its POR threshold to indicate
that the volatile memory and device settings are in their default state. The CONFIG_PRESET bit within the
STATUS_MFR_SPECIFIC register (80h) indicates default configuration of warning thresholds and device
operation and will remain set until a CLEAR_FAULTS command is received.
Figure 32. Power Up Sequence (Current Limit Only)
Copyright © 2012–2013, Texas Instruments Incorporated Submit Documentation Feedback 15
Product Folder Links: LM25066I LM25066IA