Datasheet

LOAD
VIN
GND
GND
LIVE POWER
SOURCE
PLUG - IN BOARD
V
SYS
PGD
OUT
R
S
Q1
C
L
V
OUT
LM25061
+12V
LM25061
www.ti.com SNVS611E –FEBRUARY 2011–REVISED MARCH 2013
Functional Description
The LM25061 is designed to control the in-rush current to the load upon insertion of a circuit card into a live
backplane or other "hot" power source, thereby limiting the voltage sag on the backplane’s supply voltage, and
the dV/dt of the voltage applied to the load. Effects on other circuits in the system are minimized, preventing
possible unintended resets. A controlled shutdown when the circuit card is removed can also be implemented
using the LM25061. In addition to a programmable current limit, the LM25061 monitors and limits the maximum
power dissipation in the series pass device to maintain operation within the device Safe Operating Area (SOA).
Either current limiting or power limiting for an extended period of time results in the shutdown of the series pass
device. In this event, the LM25061-1 latches off until the circuit is re-enabled by external control, while the
LM25061-2 automatically restarts with defined timing. The circuit breaker function quickly switches off the series
pass device upon detection of a severe over-current condition. The Power Good (PGD) output pin indicates
when the output voltage is above the programmed threshold. A programmable under-voltage lock-out (UVLO)
circuit enables the LM25061 when the system input voltage is above the desired threshold. The typical
configuration of a circuit card with LM25061 hot swap protection is shown in Figure 22.
Figure 22. LM25061 Application
Power Up Sequence
The VIN operating range of the LM25061 is +2.9V to +17V, with a transient capability to 20V. Referring to the
Block Diagram and Figure 21 and Figure 23, as the voltage at VIN initially increases, the external N-channel
MOSFET (Q1) is held off by an internal 260 mA pull-down current at the GATE pin. The strong pull-down current
at the GATE pin prevents an inadvertent turn-on as the MOSFET’s gate-to-drain (Miller) capacitance is charged.
Additionally, the TIMER pin is initially held at ground. When the VIN voltage reaches the POR threshold the
insertion time begins. During the insertion time, the capacitor at the TIMER pin (C
T
) is charged by a 5.5 µA
current source, and Q1 is held off by a 2 mA pull-down current at the GATE pin regardless of the VIN voltage.
The insertion time delay allows ringing and transients at VIN to settle before Q1 is enabled. The insertion time
ends when the TIMER pin voltage reaches 1.72V. C
T
is then quickly discharged by an internal 2 mA pull-down
current. The GATE pin then switches on Q1 when V
SYS
exceeds the UVLO threshold. If V
SYS
is above the UVLO
threshold at the end of the insertion time, Q1 switches on at that time. The GATE pin charge pump sources 20
µA to charge Q1’s gate capacitance. The maximum voltage at the GATE pin is limited by an internal 19.5V zener
diode.
As the voltage at the OUT pin increases, the LM25061 monitors the drain current and power dissipation of
MOSFET Q1. In-rush current limiting and/or power limiting circuits actively control the current delivered to the
load. During the in-rush limiting interval (t2 in Figure 23) an internal 80 µA fault timer current source charges C
T
.
If Q1’s power dissipation and the input current reduce below their respective limiting thresholds before the
TIMER pin reaches 1.72V the 80 µA current source is switched off, and C
T
is discharged by the internal 2.5 µA
current sink (t3 in Figure 23). The in-rush limiting interval is complete when the load current reduces to the
normal operating level. The PGD pin switches high when the output voltage exceeds the threshold programmed
at the FB pin.
If the TIMER pin voltage reaches 1.72V before in-rush current limiting or power limiting ceases (during t2), a fault
is declared and Q1 is turned off. See the Fault Timer & Restart section for a complete description of the fault
mode.
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