Datasheet

LM25061
SNVS611E –FEBRUARY 2011–REVISED MARCH 2013 www.ti.com
If a delay is required at PGD, suggested circuits are shown in Figure 35. In Figure 35a, capacitor C
PG
adds delay
to the rising edge, but not to the falling edge. In Figure 35b, the rising edge is delayed by R
PG1
+ R
PG2
and C
PG
,
while the falling edge is delayed a lesser amount by R
PG2
and C
PG
. Adding a diode across R
PG2
(Figure 35c)
allows for equal delays at the two edges, or a short delay at the rising edge and a long delay at the falling edge.
Design-in Procedure
The recommended design-in procedure is as follows:
• Determine the current limit threshold (I
LIM
). This threshold must be higher than the normal maximum load
current, allowing for tolerances in the current sense resistor value and the LM25061 Current Limit threshold
voltage. Use Equation 1 to determine the value for R
S
.
• Determine the maximum allowable power dissipation for the series pass FET (Q1), using the device’s SOA
information. Use Equation 2 to determine the value for R
PWR
.
• Determine the value for the timing capacitor at the TIMER pin (C
T
) using Equation 8 or Equation 9. The fault
timeout period (t
FAULT
) must be longer than the circuit’s turn-on-time. The turn-on time can be estimated using
the equations in the TURN-ON TIME section of this data sheet, but should be verified experimentally. Review
the resulting insertion time, and restart timing if the LM25061-2 is used.
• Choose option A or B from the UVLO section of the Application Information for setting the UVLO threshold
and hysteresis. Use the procedure for the appropriate option to determine the resistor values at the UVLO
pin.
• Choose the appropriate voltage, and pull-up resistor, for the Power Good output.
• Determine the resistor values for the FB pin.
PC Board Guidelines
The following guidelines should be followed when designing the PC board for the LM25061:
• Place the LM25061 close to the board’s input connector to minimize trace inductance from the connector to
the FET.
• Place a small capacitor (1000 pF) directly adjacent to the VIN and GND pins of the LM25061 to help minimize
transients which may occur on the input supply line. Transients of several volts can easily occur when the
load current is shut off.
• The sense resistor (R
S
) should be close to the LM25061, and connected to it using the Kelvin techniques
shown in Figure 27.
• The high current path from the board’s input to the load (via Q1), and the return path, should be parallel and
close to each other to minimize loop inductance.
• The ground connection for the various components around the LM25061 should be connected directly to
each other, and to the LM25061’s GND pin, and then connected to the system ground at one point. Do not
connect the various component grounds to each other through the high current ground line.
• Provide adequate heat sinking for the series pass device (Q1) to help reduce stresses during turn-on and
turn-off.
• The board’s edge connector can be designed to shut off the LM25061 as the board is removed, before the
supply voltage is disconnected from the LM25061. In Figure 36 the voltage at the UVLO pin goes to ground
before V
SYS
is removed from the LM25061 due to the shorter edge connector pin. When the board is inserted
into the edge connector, the system voltage is applied to the LM25061’s VIN pin before the UVLO voltage is
taken high.
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