Datasheet
VIN
UVLO/
EN
GND
TIMER AND GATE
LOGIC CONTROL
LM25061
V
PWR
20 PA
1.17V
V
UVL
=
1.17V x (R1 + R2)
R2
V
UVH
= 1.17V + [R1 x
R2
(1.17V + 20 PA)]
R2 =
1.17V x R1
V
UVL
- 1.17V
R1 =
V
UVH
- V
UVL
20 PA
=
V
UV(HYS)
20 PA
VIN
UVLO/
EN
GND
R1
TIMER AND GATE
LOGIC CONTROL
LM25061
V
PWR
20 PA
1.17V
R2
LM25061
SNVS611E –FEBRUARY 2011–REVISED MARCH 2013
www.ti.com
Figure 31. Programming the UVLO Thresholds
The two resistor values are calculated as follows:
• Choose the upper and lower UVLO thresholds (V
UVH
) and (V
UVL
).
(11)
(12)
As an example, assume the application requires the following thresholds: V
UVH
= 8V, V
UVL
= 7V.Therefore
V
UV(HYS)
= 1V. The resistor values are:
R1 = 50 kΩ, R2 = 10 kΩ (13)
Where the resistor values are known, the threshold voltages and hysteresis are calculated from the following:
(14)
(15)
V
UV(HYS)
= R1 x 20 µA (16)
Option B: The minimum UVLO level is obtained by connecting the UVLO pin to VIN as shown in Figure 32. Q1
is switched on when the VIN voltage reaches the POR threshold (≊2.6V).
Figure 32. UVLO = POR
18 Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated
Product Folder Links: LM25061