Datasheet
t
ON
=
C
L
x V
SYS
2
2 x P
FET(LIM)
C
L
x P
FET(LIM)
2 x I
LIM
2
+
VIN
GND
PGD
OUT
Q1
GND
LM25061
V
SYS
C
L
R
L
R
S
VIN
GND
PGD
OUT
Q1
GND
V
SYS
C
L
R
L
R
S
LM25061
t
ON
= -(R
L
x C
L
) x In
(I
LIM
x R
L
) - V
SYS
(I
LIM
x R
L
)
LM25061
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SNVS611E –FEBRUARY 2011–REVISED MARCH 2013
For example, if V
SYS
= 12V, C
L
= 1000 µF, and I
LIM
= 1A, t
ON
calculates to 12 ms. The maximum instantaneous
power dissipated in the MOSFET is 12W. This calculation assumes the time from t1 to t2 in Figure 30a is small
compared to t
ON
, and the load does not draw any current until after the output voltage has reached its final value,
(Figure 28). If the load draws current during the turn-on sequence (Figure 29), the turn-on time is longer than the
above calculation, and is approximately equal to:
where
• R
L
is the load resistance (5)
The Fault Timeout Period must be set longer than t
ON
to prevent a fault shutdown before the turn-on sequence is
complete.
Figure 28. No Load Current During Turn-On
Figure 29. Load Draws Current During Turn-On
B) Turn-on with power limit and current limit: The maximum allowed power dissipation in Q1 (P
FET(LIM)
) is
defined by the resistor at the PWR pin, and the current sense resistor R
S
. See the Power Limit Threshold
section. If the current limit threshold (I
LIM
) is higher than the current defined by the power limit threshold at
maximum V
DS
(P
FET(LIM)/
V
SYS
) the circuit operates initially in the power limit mode when the V
DS
of Q1 is high,
and then transitions to current limit mode as the current increases to I
LIM
and V
DS
decreases. See Figure 30b.
Assuming the load (R
L
) is not connected during turn-on, the time for the output voltage to reach its final value is
approximately equal to:
(6)
For example, if V
SYS
= 12V, C
L
= 1000 µF, I
LIM
= 1A, and P
FET(LIM)
= 10W, t
ON
calculates to ≊12.2 ms, and the
initial current level (I
P
) is approximately 0.83A. The Fault Timeout Period must be set longer than t
ON
.
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