Datasheet

UVLO
COMP
FB
RT2
AGND
RT1
CS
RAMP
VCC
OUTA
OUTB
PGND
SS
RES
REF
VIN
LM25037
14
13
12
11
10
8 9
15
16
1
2
3
4
5
7
6
LM25037, LM25037-Q1
SNVS572D –JULY 2008–REVISED MARCH 2013 www.ti.com
Connection Diagram
Figure 1. Top View
16-Lead TSSOP Package
See PW Package
PIN DESCRIPTIONS
Pin Name Description Application Information
1 RAMP Pulse width modulator ramp Modulation ramp for the PWM comparator. This ramp can be a representative
of the primary current (current mode) or proportional to input voltage (feed-
forward voltage mode). This pin is reset to ground at the conclusion of every
cycle by an internal FET.
2 UVLO Line under-voltage lockout An external voltage divider from the power source sets the shutdown and
standby comparator threshold levels. When UVLO exceeds the 0.45V
shutdown threshold, the VCC and REF regulators are enabled. When UVLO
exceeds the 1.25V standby threshold, the SS pin is released and the device
enters the active mode.
3 COMP Input to the pulse width modulator Output of the error amplifier and input to the PWM comparator.
4 FB Feedback Connected to inverting input of the error amplifier. An internal 1.25V reference
is connected to the non-inverting input of the error amplifier. In isolated
applications using an external error amplifier, this pin should be connected to
the AGND pin.
5 RT2 Oscillator dead-time control The resistance connected between RT2 and AGND sets the forced dead-time
between switching periods of the alternating outputs.
6 AGND Analog ground Connect directly to Power Ground.
7 RT1 Oscillator maximum on-time control The resistance connected between RT1 and AGND sets the oscillator
maximum on-time. The sum of this maximum on-time and the forced dead-time
(set by RT2) sets the oscillator period.
8 CS Current sense input If CS exceeds 250 mV the output pulse will be terminated, entering cycle-by-
cycle current limit. An internal switch holds CS low for 65 nS after either output
switches high to blank leading edge transients.
9 RES Restart timer If cycle-by-cycle current limit is reached during any cycle, a 18 µA current is
sourced to the external RES pin capacitor. If the RES capacitor voltage
reaches 2.0V, the soft-start capacitor will be fully discharged and then released
with a pull-up current of 1 uA. After the first output pulse (when SS = 1V), the
SS pin charging current will increase to the normal level of 100 µA.
10 SS Soft-start An external capacitor and an internal 100uA current source set the soft-start
ramp. The SS current source is reduced to 1 µA following a restart event (RES
pin high).
11 PGND Power ground Connect directly to Analog Ground
12 OUTB Output driver Alternating gate drive output of the pulse width modulator. Capable of 1.2A
peak source and sink current.
13 OUTA Output driver Alternating gate drive output of the pulse width modulator. Capable of 1.2A
peak source and sink current.
14 VCC Output of the high voltage start-up If an auxiliary winding raises the voltage on this pin above the regulation set
regulator. The VCC voltage is point, the internal start-up regulator will shutdown thus reducing the IC power
regulated to 7.7V. dissipation. Locally decouple VCC with a 0.47 µF or greater capacitor.
15 REF Output of a 5V reference Locally decouple with a 0.1 µF or greater capacitor. Maximum output current is
10 mA (typ).
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