Datasheet

CLK
OUTA
OUTB
T
Dead-Time
T
Dead-Time
D RT2
T
onmax
D RT1
T
Dead-Time
T
onmax
T
osc
RT1 =
- (Dead-Time)
0.162 x 10
-9
1
F
OSC
RT2 =
Dead-Time
5.0 x 10
-12
50 ns<DT<250 ns
or
RT2 =
(1 - D
max
) / F
OSC
5.0 x 10
-12
LM25037, LM25037-Q1
www.ti.com SNVS572D –JULY 2008–REVISED MARCH 2013
(1)
It is recommended to set the dead-time range between 50 ns and 250 ns. Beyond 250 ns, RT2 becomes
excessively large, and is prone to noise pickup. Fixed internal delays limit the dead-time to greater than 50 ns.
After the dead-time has been programmed by RT2, the overall oscillator frequency can be set by selecting
resistor RT1 from :
(2)
For example, if the desired oscillator frequency is 400 kHz (OUTA and OUTB each switching at 200 kHz) and
desired dead-time is 100 ns, the maximum duty cycle for each output will be 96% and the values of RT1 and
RT2 will be 15 kΩ and 20 kΩ respectively.
Figure 20. Timing Diagram of OUTA, OUTB and Dead-Time Set by RT2
As shown in Figure 20, the internal clock pulse width is the same as the dead-time set by RT2. This dead-time
pulse is used to limit the maximum duty cycle for each of the outputs. Also, the discharge FET connected to the
RAMP pin is enabled during the dead-time every clock period. The voltages at both the RT1 and RT2 pins are
internally regulated to a nominal 2V. Both the resistors RT1 and RT2 should be located as close as possible to
the IC, and connected directly to the pins. The tolerance of the external resistors and the frequency tolerance
indicated in Electrical Characteristics must be taken into account when determining the worst case frequency
range.
SYNC CAPABILITY
The LM25037 can be synchronized to an external clock by applying a narrow ac pulse to the RT1 pin. The
external clock must be at least 10% higher than the free-running oscillator frequency set by the RT1 and RT2
resistors. If the external clock frequency is less than the programmed frequency, the LM25037 will ignore the
synchronizing pulses. The synchronization pulse width at the RT1 pin must be a minimum of 15 ns wide. The
synchronization signal should be coupled into the RT1 pin through a 100 pF capacitor or another value small
enough to ensure the sync pulse width at RT1 is less than 60% of the clock period under all conditions. When
the synchronizing pulse transitions from low-to-high (rising edge), the voltage at the RT1 pin must be driven to
exceed 3.0V from its nominal 2.0V volt dc level. During the synchronization clock signal’s low time, the voltage at
the RT1 pin will be clamped at 2V volts by an internal regulator. The RT1 and RT2 resistors are always required,
whether the oscillator is free running or externally synchronized.
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