Datasheet

I
PK
=
R
CL
1.5A x (150 m: + R
CL
)
+ I
OR(MAX)
R
CL
=
1.0A x 0.11:
I
PK-
- 1.0A
I
PK-
= I
O(max)
-
2
I
OR(min)
LM25010
www.ti.com SNVS419D –DECEMBER 2005–REVISED FEBRUARY 2013
To reduce V
OUT
ripple further, the circuit of Figure 17 can be used. R3 has been removed, and the output ripple
amplitude is determined by C2’s ESR and the inductor ripple current. RA and CA are chosen to generate a 40 to
50 mV
P-P
sawtooth at their junction, and that voltage is AC-coupled to the FB pin via CB. In selecting RA and CA,
V
OUT
is considered a virtual ground as the SW pin switches between V
IN
and –1V. Since the on-time at SW
varies inversely with V
IN
, the waveform amplitude at the RA/CA junction is relatively constant. R1 and R2 must
typically be increased to more than 5kΩ each to not significantly attenuate the signal provided to FB through CB.
Typical values for the additional components are RA = 200kΩ, CA = 680 pF, and CB = 0.01 µF.
Increasing The Current Limit Threshold
The current limit threshold is nominally 1.25A, with a minimum guaranteed value of 1.0A. If, at maximum load
current, the lower peak of the inductor current (I
PK-
in Figure 11) exceeds 1.0A, resistor R
CL
must be added
between SGND and ISEN to increase the current limit threshold to equal or exceed that lower peak current. This
resistor diverts some of the recirculating current from the internal sense resistor so that a higher current level is
needed to switch the internal current limit comparator. I
PK–
is calculated from:
(24)
where I
O(max)
is the maximum load current, and I
OR(min)
is the minimum ripple current calculated using
Equation 20. R
CL
is calculated from:
(25)
where 0.11Ω is the minimum value of the internal resistance from SGND to ISEN. The next smaller standard
value resistor should be used for R
CL
. With the addition of R
CL
, and when the circuit is in current limit, the upper
peak current out of the SW pin (I
PK
in Figure 10) can be as high as:
(26)
where I
OR(max)
is calculated using Equation 14. The inductor L1 and diode D1 must be rated for this current. If I
PK
exceeds 2A , the inductor value must be increased to reduce the ripple amplitude. This will necessitate
recalculation of I
OR(min)
, I
PK–
, and R
CL
.
Increasing the circuit’s current limit will increase power dissipation and the junction temperature within the
LM25010. See the next section for guidelines on this issue.
PC Board Layout and Thermal Considerations
The LM25010 regulation, over-voltage, and current limit comparators are very fast, and will respond to short
duration noise pulses. Layout considerations are therefore critical for optimum performance. The layout must be
as neat and compact as possible, and all the components must be as close as possible to their associated pins.
The two major current loops have currents which switch very fast, and so the loops should be as small as
possible to minimize conducted and radiated EMI. The first loop is that formed by C1, through the VIN to SW
pins, L1, C2, and back to C1. The second loop is that formed by D1, L1, C2, and the SGND and ISEN pins. The
ground connection from C2 to C1 should be as short and direct as possible, preferably without going through
vias. Directly connect the SGND and RTN pin to each other, and they should be connected as directly as
possible to the C1/C2 ground line without going through vias. The power dissipation within the IC can be
approximated by determining the total conversion loss (P
IN
– P
OUT
), and then subtracting the power losses in the
free-wheeling diode and the inductor. The power loss in the diode is approximately:
P
D1
= I
O
× V
F
× (1 – D) (27)
where I
O
is the load current, V
F
is the diode’s forward voltage drop, and D is the duty cycle. The power loss in the
inductor is approximately:
P
L1
= I
O
2
× R
L
× 1.1 (28)
where R
L
is the inductor’s DC resistance, and the 1.1 factor is an approximation for the AC losses. If it is
expected that the internal dissipation of the LM25010 will produce high junction temperatures during normal
operation, good use of the PC board’s ground plane can help considerably to dissipate heat. The exposed pad
on the IC package bottom should be soldered to a ground plane, and that plane should both extend from
beneath the IC, and be connected to exposed ground plane on the board’s other side using as many vias as
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