Datasheet
SYNC
10k
S
R
Q
Q
DEADTIME
ONE-SHOT
5V
2.5V
I = f(RT)
LM25005
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SNVS411C –JANUARY 2006–REVISED MARCH 2013
Figure 12. Simplified Oscillator Block Diagram and SYNC I/O Circuit
Error Amplifier and PWM Comparator
The internal high gain error amplifier generates an error signal proportional to the difference between the
regulated output voltage and an internal precision reference (1.225V). The output of the error amplifier is
connected to the COMP pin allowing the user to provide loop compensation components, generally a type II
network, as illustrated in Typical Application Circuit and Block Diagram. This network creates a pole at DC, a
zero and a noise reducing high frequency pole. The PWM comparator compares the emulated current sense
signal from the RAMP generator to the error amplifier output voltage at the COMP pin.
RAMP Generator
The ramp signal used in the pulse width modulator for current mode control is typically derived directly from the
buck switch current. This switch current corresponds to the positive slope portion of the output inductor current.
Using this signal for the PWM ramp simplifies the control loop transfer function to a single pole response and
provides inherent input voltage feed-forward compensation. The disadvantage of using the buck switch current
signal for PWM control is the large leading edge spike due to circuit parasitics that must be filtered or blanked.
Also, the current measurement may introduce significant propagation delays. The filtering, blanking time and
propagation delay limit the minimum achievable pulsewidth. In applications where the input voltage may be
relatively large in comparison to the output voltage, controlling small pulsewidths and duty cycles is necessary for
regulation. The LM25005 utilizes a unique ramp generator, which does not actually measure the buck switch
current but rather reconstructs the signal. Reconstructing or emulating the inductor current provides a ramp
signal to the PWM comparator that is free of leading edge spikes and measurement or filtering delays. The
current reconstruction is comprised of two elements; a sample & hold DC level and an emulated current ramp.
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