Datasheet

LM22671

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SNVS589M –SEPTEMBER 2008–REVISED APRIL 2013

The choice of switching frequency is governed by several considerations. As an example, lower frequencies may

be desirable to reduce switching losses or improve duty cycle limits. Higher frequencies, or a specific frequency,

may be desirable to avoid problems with EMI or reduce the physical size of external components. The flexibility

of increasing the switching frequency above 500 kHz can also be used to operate outside a critical signal

frequency band for a given application. Keep in mind that the values of inductor and output capacitor cannot be

reduced dramatically, by operating above 500 kHz. This is true because the design of the internal loop

compensation restricts the range of these components.

Frequency synchronization requires some care. First the external clock frequency must be greater than the

internal clock frequency, and less than 1 MHz. The maximum internal switching frequency is ensured in the

Electrical Characteristics table. Note that the frequency adjust feature and the synchronization feature can not be

used simultaneously. The synchronizing frequency must always be greater than the internal clock frequency.

Secondly, the RT/SYNC pin must see a valid high or low voltage, during start-up, in order for the regulator to go

into the synchronizing mode (see above). Also, the amplitude of the synchronizing pulses must comport with

SYNC

levels found in the Electrical Characteristics table. The regulator will synchronize on the rising edge of the

external clock. If the external clock is lost during normal operation, the regulator will revert to the 500 kHz (typ.)

internal clock.

If the frequency synchronization feature is used, current limit foldback is not operational; see the Current Limit

section for details.

Figure 18. Switching Frequency vs RT/SYNC Resistor

Self Synchronization

It is possible to synchronize multiple LM22671 regulators together to share the same switching frequency. This

can be done by tieing the RT/SYNC pins together through a MOSFET and connecting a 1 KΩ resistor to ground

at each pin. Figure 19 shows this connection. The gate of the MOSFET should be connected to the regulator

with the highest output voltage. Also, the EN pins of both regulators should be tied to the common system

enable, in order to properly initialize both regulators. The operation is as follows: When the regulators are

enabled, the outputs are low and the MOSFET is off. The 1 kΩ resistors pull the RT/SYNC pins low, thus

enabling the synchronization mode. These resistors are small enough to pull the RT/SYNC pin low, rather than

activate the frequency adjust mode. Once the output voltage of one of the regulators is sufficient to turn on the

MOSFET, the two RT/SYNC pins are tied together and the regulators will run in synchronized mode. The two

regulators will be clocked at the same frequency but slightly phase shifted according to the minimum off-time of

the regulator with the fastest internal oscillator. The slight phase shift helps to reduce stress on the input

capacitors of the regulator. It is important to choose a MOSFET with a low gate threshold voltage so that the

MOSFET will be fully enhanced. Also, a MOSFET with low inter-electrode capacitance is required. The 2N7002

is a good choice.

Product Folder Links: LM22671