Datasheet

Exposed Pad
Connect to GND
5 RT/SYNC
6 FB
3 BOOT
1 SW
2 VIN
4 GND
7 EN
Exposed Pad
Connect to GND
RT/SYNC
3
FB
4
BOOT
1
NC
2
8
SW
7
VIN
6
GND
5
EN
LM22670-ADJ
VIN
EN
SW
BOOT
FB
GND
VIN
VOUT
RT/SYNC
LM22670
SNVS584O –SEPTEMBER 2008–REVISED MARCH 2013 www.ti.com
Simplified Application Schematic
Connection Diagram
Figure 1. 8-Lead SO PowerPAD-8 Package
See Package Number DDA0008B
Figure 2. 7-Lead PFM Package
See Package Number NDR0007A
PIN DESCRIPTIONS
Pin Numbers
SO Pin Numbers
Name Description Application Information
PowerPAD-8 PFM Package
Package
1 3 BOOT Bootstrap input Provides the gate voltage for the high side NFET.
2 - NC Not Connected Pin is not electrically connected inside the chip. Pin does
function as thermal conductor.
2 Submit Documentation Feedback Copyright © 2008–2013, Texas Instruments Incorporated
Product Folder Links: LM22670