Datasheet

LM21305
SNVS639F –DECEMBER 2009–REVISED MARCH 2013 www.ti.com
ESD Ratings
All pins, Human Body Model
(1)
±2kV
(1) The Human Body Model is a 100 pF capacitor discharged through a 1.5 kΩ resistor into each pin (MIL-STD-883 3015.7).
Operating Ratings
PVIN to PGND, AGND 3V to 18V
AVIN to PGND, AGND 3V to 18V
Junction Temperature −40°C to 125°C
Ambient Temperature
(1)
−40°C to 85°C
Junction-to-Ambient Thermal Resistance θ
JA
(2)
32.4°C/W
(1) In applications where high power dissipation and/or poor package thermal resistance is present, the maximum ambient temperature may
have to be de-rated. Maximum ambient temperature (T
A-MAX
) is dependent on the maximum operating junction temperature (T
J-MAX-OP
=
125°C), the maximum power dissipation of the device in the application (P
D-MAX
), and the junction-to ambient thermal resistance of the
part/package in the application (θ
JA
), as given by the following equation: T
A-MAX
= T
J-MAX-OP
– (θ
JA
× P
D-MAX
).
(2) Junction-to-ambient thermal resistance (θ
JA
) is taken from a thermal modeling result, performed under the conditions and guidelines set
forth in the JEDEC standard JESD51-7. The test board is a 4-layer standard JEDEC thermal test board or 4LJEDEC, 4" x 3" in size,
with a 3 by 3 array of thermal vias. The board has two embedded copper layers which cover roughly the same size as the board. The
copper thickness for the four layers, starting from the top one, is 2 oz./1oz./1oz./2 oz. For WQFN, thermal vias are placed between the
die attach pad in the 1st. copper layer and 2nd. copper layer. Detailed description of the board can be found in JESD 51-7. Ambient
temperature in the simulation is 22°C, still air. Power dissipation is 1W. The value of θ
JA
of this product can vary significantly depending
on PCB material, layout, and environmental conditions. In applications with high power dissipation (e.g. high V
OUT
, high I
OUT
), special
care must be paid to thermal dissipation issues. For more information on these topics, please refer to Application Note AN-1187:
Leadless Leadframe Package (LLP) (literature number SNOA401).
Electrical Characteristics
(1) (2)(2)
Specifications with standard typeface are for T
J
= 25°C, and those in boldface type apply over the full Operating
Temperature Range (T
J
= -40°C to +125°C). Unless otherwise specified, V
IN
= V
PVIN
= V
AVIN
= 12V, V
OUT
= 3.3V, I
OUT
= 0A.
Symbol Parameter Remarks Min Typ Max Unit
Feedback pin factory-default
V
FB-default
0.588 0.598 0.608 V
voltage
ΔV
OUT
/ΔI
OUT
Load Regulation I
OUT
= 0.1A to 5A 0.02 %/A
ΔV
OUT
/ΔV
IN
Line Regulation V
PVIN
= 3V to 18V 0.01 %/V
High-Side Switch On
R
DSonHS
I
DS
= 5A 44 mΩ
Resistance
Low-Side Switch On
R
DSonLS
I
DS
= 5A 22 mΩ
Resistance
I
CL-HS
High-Side Switch Current Limit High-side FET 5.9 7.0 7.87 A
I
CL-LS
Low-Side Switch Current Limit Low-side FET
(3)
5.9 8.0 10.2 A
Low-Side Switch Negative
I
NEG-CL-LS
Low-side FET -7.0 -4.1 -1.64 A
Current Limit
V
AVIN
= V
PVIN
= 5V 0.1 2
I
SD
Quiescent Current, disabled µA
V
AVIN
= V
PVIN
= 18V 1 4.1
Quiescent Current, enabled,
I
Q
V
AVIN
= V
PVIN
= 18V 9 9.7 mA
not switching
Feedback Pin Input Bias
I
FB
V
FB
= 0.598V 1 nA
Current
Error Amplifier
G
M
2400 µS
Transconductance
A
VOL
Error Amplifier Voltage Gain 65 dB
Output voltage rising threshold,
V
IH-OVP
OVP Tripping Threshold 103.5 109.5 115 %
percentage of V
OUT
V
HYST-OVP
OVP Hysteresis Window Percentage of V
OUT
-4.3 %
(1) All limits are specified by design, test and/or statistical analysis. All electrical characteristics having room-temperature limits are tested
during production with T
J
= 25°C. All hot and cold limits are specified by correlating the electrical characteristics to process and
temperature variations and applying statistical process control.
(2) Capacitors: low ESR surface-mount ceramic capacitors (MLCCs) are used in setting electrical characteristics.
(3) The low-side switch current limit is ensured to be higher than the high-side current limit.
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