Datasheet

LM21305
www.ti.com SNVS639F –DECEMBER 2009–REVISED MARCH 2013
PIN DESCRIPTIONS
Number Name Type
(1)
Pad Description
1,2,27,28 PVIN P Input voltage to the power switches inside the device.
3,4,5,6 SW P Switch node output of the power switches. Voltage swings from PVIN to GND on this
pin. SW also delivers current to the external inductor.
7,8,9,10 PGND G Power ground for the internal power switches.
11 COMP A Compensation pin to connect to external compensation network.
12 PGOOD OD Power Good, open-drain output. If high, indicates the output voltage is regulated within
tolerance. A pull-up resistor (10 kΩ to 100 kΩ) is recommended for most applications.
13 FB A Voltage Feedback pin. This pin can be connected to the output voltage directly or
through a resistor divider to set the output voltage range.
14,17,18,19,20,24 AGND G Analog ground for the internal bias circuitry.
15 EN I Precision enable pin. An external divider can be used to set the device turn-on
threshold. If not used, the EN pin should be connected to AVIN.
16 FREQ A Frequency setting pin. This pin can be connected to a resistor to AGND to set the
internal oscillator frequency. It also can be connected to an external clock source via a
capacitor such that the switching frequency of the device is synchronized to the
external clock.
21 2V5 P 2.5V output of internal regulator. This pin is only for bypassing the internal LDO.
Loading this pin is not recommended.
22,23 AVIN P Analog power input. AVIN powers the internal 2.5V and 5.0V LDOs which provide bias
current and internal driver power. It can be connected to PVIN through a low pass RC
filter or can be supplied by a separate rail.
25 5V0 P 5.0V output of internal regulator. This pin is only for bypassing the internal LDO.
Loading this pin is not recommended.
26 CBOOT A Bootstrap pin to drive the high-side switch. A bootstrap capacitor should be connected
between this pin and the SW pin.
PAD PAD Exposed pad at the back of the device. The PAD should be connected to PGND, but
cannot be used as primary ground connection. Use multiple vias under the PAD for
optimal thermal performance.
(1) P: Power, A: Analog, I: Digital Input, OD: Open Drain, G: Ground
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
Absolute Maximum Ratings
(1)(2)
PVIN, AVIN, SW, EN, PGOOD to AGND −0.3V to +20V
CBOOT to AGND −0.3V to +25V
CBOOT to SW −0.3V to +5.5V
5V0, FB, COMP, FREQ to AGND −0.3V to +6V
2V5 to AGND −0.3V to +3V
AGND to PGND −0.3V to +0.3V
Junction Temperature (T
J-MAX
) 150°C
Storage Temperature Range −65°C to 150°C
Maximum Continuous Power Dissipation P
D-MAX
(3)
Internally limited
Maximum Lead Temperature Lead-free Compatible
(4)
260°C
(1) Absolute Maximum Ratings are limits beyond which damage to the device may occur. Operating Ratings are conditions under which
operation of the device is ensured. Operating Ratings do not imply specified performance limits. For specified performance limits and
associated test conditions, see the Electrical Characteristics tables.
(2) If Military/Aerospace specified devices are required, please contact the Texas Instruments Sales Office/Distributors for availability and
specifications.
(3) The amount of Absolute Maximum power dissipation allowed in the device depends on the ambient temperature and can be calculated
using the formula P = (T
J
– T
A
)/θ
JA
, where T
J
is the junction temperature, T
A
is the ambient temperature and θ
JA
is the junction-to-
ambient thermal resistance. Junction-to-ambient thermal resistance is highly application and board-layout dependent. In applications
where high power dissipation exists, special care must be paid to thermal dissipation issues in PC board design. Internal thermal
shutdown circuitry protects the device from permanent damage.
(4) For detailed soldering specifications, please refer to Application Note AN-1187: Leadless Leadframe Package (LLP) (literature number
SNOA401).
Copyright © 2009–2013, Texas Instruments Incorporated Submit Documentation Feedback 3
Product Folder Links: LM21305