Datasheet

LM21305
www.ti.com SNVS639F –DECEMBER 2009–REVISED MARCH 2013
PCB LAYOUT CONSIDERATIONS
PC board layout is an important and critical part of any DC-DC converter design. Poor PC board layout can
disrupt the performance of a DC-DC converter and surrounding circuitry by contributing to EMI, ground bounce,
resistive voltage loss in the traces, and thermal problems. Erroneous signals can reach the DC-DC converter,
possibly resulting in poor regulation or instability.
Good PCB layout with an LM21305-based converter can be implemented by following a few simple design rules.
1. Provide adequate device heat sinking by utilizing the PCB ground planes as the primary thermal path. As
such, the use of thermal vias facilitates the transfer of heat from the LM21305 into the system board. Use at
least a 4-layer PCB with the copper thickness for the four layers, starting from the top layer, of 2
oz/1oz/1oz/2 oz. Use a 3 by 3 array of 10mil thermal vias to connect the DAP to the system ground plane
heat sink. The vias should be evenly distributed under the DAP. The system ground planes should
predominately be PGND planes (representing input and output capacitor return paths, input and output DC
current return paths, etc.).
2. It is imperative that the input capacitors are located as close as possible to the PVIN and PGND pins; the
inductor should be placed as close as possible to the SW pins and output capacitors. This is to minimize the
area of switching current loops and reduce the resistive loss of the high current path. Based the LM21305
pinout, a 1 µF to 10 µF ceramic capacitor can be placed right by pins 1, 2 and pin 7, across the SW node
trace, as an addition to the bulk input capacitors. Using a size 1206 or 1210 capacitor allows enough copper
width for the switch node to be routed underneath the capacitor for good conduction (see LM21305
evaluation board layout detailed in Application Note AN-2042 (literature number SNVA432)).
3. The copper area of the switch node should be thick and short to both provide a good conduction path for the
switch node current to the inductor and to minimize radiated EMI. This also requires the inductor be placed
as close as possible to the SW pins.
4. The feedback trace from VOUT to the feedback divider resistors should be routed away from the SW pin and
inductor to avoid contaminating this feedback signal with switch noise. This is most important when high
resistances are used to set the output voltage. It is recommended to route the feedback trace on a different
layer than the inductor and SW node trace such that a ground plane exists between the feedback trace and
inductor/SW node polygon. This provides further cancellation of EMI on the feedback trace.
5. If voltage accuracy at the load is important, make sure feedback voltage sense is made directly at the load
terminals. Doing so will correct for voltage drops in the PCB planes and traces and provide optimal output
voltage setpoint accuracy and load regulation. It is always better to place the resistor divider closer to the FB
node, rather than close to the load, as the FB node is the input to the error amplifier and is thus noise
sensitive. COMP is also a noise sensitive node and the compensation components should be located as
close as possible to the IC.
6. Make input and output power bus connections as wide and short as possible. This reduces any voltage
drops on the input or output of the converter and can improve efficiency. Use copper plates/planes on top to
connect the multiple PVIN pins and PGND pins together.
7. The 0.1 µF boot capacitor connected between the CBOOT pin and SW node should be placed as close as
possible to the CBOOT and SW pins.
8. The frequency set resistor and its associated capacitor should be placed as close as possible to the FREQ
pin.
Thermal Considerations
The thermal characteristics of the LM21305 are specified using the parameter θ
JA
, which relates junction
temperature to ambient temperature in a particular LM21305 application. Although the value of θ
JA
is dependent
on many variables, it still can be used to approximate the operating junction temperature of the device.
To obtain an estimate of the device junction temperature, one may use the following relationship: T
J
= P
D
θ
JA
+ T
A
where
P
D
= P
IN
x (1 − Efficiency) − 1.1 x I
OUT
2
x R
dcr
T
J
= Junction temperature of the LM21305 in °C
P
IN
= Input power in Watts (P
IN
= V
IN
x I
IN
)
θ
JA
= Junction-to-ambient thermal resistance of the LM21305 in °C/W
T
A
= Ambient temperature in °C
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