Datasheet

 = 1 -
Total Power Loss
Input Power
LM21305
www.ti.com SNVS639F –DECEMBER 2009–REVISED MARCH 2013
One or more ceramic capacitors are generally recommended because they have very low ESR and remain
capacitive up to high frequencies. The capacitor dielectric should be X5R or X7R to maintain proper tolerance.
Other types of capacitors also can be used, particularly if large bulk capacitance is needed (such as tantalum,
POSCAP and OSCON). Such electrolytic capacitors have lower ESR zero {1/(2πESR *C
OUT
} frequency than
ceramic capacitors. The lower ESR zero frequency can influence the control loop, particularly if it occurs close to
the desired crossover frequency. If high switching frequency and high loop crossover frequency are warranted,
an all ceramic design can be more appropriate.
EFFICIENCY CONSIDERATIONS
The efficiency of a switching regulator is defined as the output power divided by the input power times 100%.
Efficiency also can be found by:
(17)
It is often useful to analyze individual losses to determine what is limiting the efficiency and what change would
produce the most improvement. Although all dissipative elements in the circuit produce losses, three main
sources usually account for most of the losses in LM21305-based converters: 1) conduction losses; 2) switching
and gate drive losses; 3) bias losses. Conduction losses are the I
2
R losses in parasitic resistances including on-
state resistances of the internal switches R
DSon
, equivalent inductor DC resistance R
dcr
, and PC board trace
resistances R
trace
. The conduction loss can be approximated by:
(18)
The total conduction loss can be reduced by reducing these parasitic resistances. For example, the LM21305 is
designed to have low R
DSon
internal MOSFET switches. The inductor DCR should be small. The traces that
conduct the current should be wide, thick and as short as possible. Obviously, the conduction losses affect the
efficiency more at heavier load.
Switching losses include all the losses generated by the switching action of the two power MOSFETs. Each time
the switch node swings from low to high or vice versa, charges are applied or removed from the parasitic
capacitance from the SW node to GND. Each time a power MOSFET gate is switched from low to high to low
again, a packet of charge moves from 5V0 to ground. Furthermore, each time a power MOSFET is turned on or
off, a transition loss is generated related to the overlap of voltage and current. MOSFET parasitic diodes
generate reverse recovery loss and dead time conduction loss. RMS currents through the input and output
capacitor ESR also generate loss. All of these losses should be evaluated and carefully considered to design a
high efficiency switching power converter. Since these losses only occur during ‘switching’, reducing the
switching frequency always helps to reduce the switching loss and the resultant improvement in efficiency is
more pronounced at lighter load.
Since the 5V0 rail is an LDO output from AVIN, the current drawn from AVIN is the same as i
Drive
and the
associated power loss is V
AVIN
* i
Drive
. The other portion of AVIN power loss is the bias current through the 2V5
rail which equals V
AVIN
* i
bias
. Powering AVIN from a 5V system rail provides an optimal tradeoff between bias
power loss and switching loss.
LOAD CURRENT DERATING WHEH DUTY CYCLE EXCEEDS 50%
The LM21305 is optimized for lower duty cycle operation, e.g. high input to output voltage ratio. The high-side
MOSFET is designed to be half the size of the low-side MOSFET thus optimizing the relative levels of switching
loss in the high-side switch and the conduction loss in the low-side switch. The continuous current rating of the
low-side switch is the maximum load current of 5A, while the high-side MOSFET is rated at 2.5A. If the LM21305
is operating with duty cycles higher than 50%, the maximum output current should be derated.
(19)
Derating of maximum load current when D > 50% is also illustrated in Figure 28.
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