Datasheet

V
OUT
(V
PVIN
- V
OUT
)
V
PVIN
I
RMS_CIN
= I
OUT
(A)
V
OUT
V
PVIN
©
§
©
§
D
ideal
=
LM21305
SNVS639F –DECEMBER 2009–REVISED MARCH 2013 www.ti.com
CALCULATING THE DUTY CYCLE
The first equation to calculate for any buck converter is duty cycle. In an ideal (no loss) buck converter, the duty
cycle can be found by:
(8)
In applications with low output voltage (<1.2V) and high load current (> 3A), the losses should not be ignored
when calculation the duty cycle. Considering the effect of conduction losses associated with the MOSFETs and
inductor, the duty cycle can be approximated by:
(9)
R
DSonHS
and R
DSonLS
are the on-state parasitic resistances of the high-side and low-side MOSFETs, respectively.
R
dcr
is the equivalent DC resistance of the inductor used in the output filter. Other parasitics, such as PCB trace
resistance, can be included if desired. I
OUT
is the load current. It is also equal to the average inductor current.
The duty cycle will increase slightly with increase of load current.
SUPPLY POWER AND INPUT CAPACITORS
PVIN is the supply voltage for the switcher power stage. It is the input source that delivers the output power to
the load. The input capacitors on the PVIN rail supply the large AC switching current drawn by the switching
action of the internal power MOSFETs. The input current of a buck converter is discontinuous and the ripple
current supplied by the input capacitor can be quite large. The input capacitor must be rated to handle this
current. To prevent large voltage transients, a low ESR input capacitor sized for the maximum RMS current
should be used. The maximum RMS current is given by:
(10)
The power dissipation of the input capacitor is given by: P
D_CIN
= I
2
RMS_CIN
R
ESR_CIN
(W) where R
ESR_CIN
is the
ESR of the input capacitor. This equation has a maximum at PVIN = 2V
OUT
, where I
RMS_CIN
≅ I
OUT
/2 and D ≅
50%. This simple worst-case condition is commonly used for design purposes because even significant
deviations from the worst case duty cycle operating point do not offer much relief. Note that ripple current ratings
from capacitor manufacturers are often based on only 2000 hours of life which makes it advisable to further
derate the capacitor, or choose a capacitor rated at a higher temperature than required. Several capacitors may
also be paralleled to meet size or height requirements in the design. For low input voltage applications, sufficient
bulk input capacitance is needed to minimize transient effects during output load current changes. A 1 µF
ceramic bypass capacitor is also recommended directly adjacent the IC between the PVIN and PGND pins.
Please refer to Figure 33 and the PCB LAYOUT CONSIDERATIONS section provided later in this document.
AVIN FILTER
An RC filter should be added to prevent any switching noise on PVIN from interfering with the internal analog
circuitry connected to AVIN. These can be seen on the schematic as components R
F
and C
F
. There is a practical
limit to the size of resistor R
F
as the AVIN pin will draw a short 60 mA burst of current during startup and if R
F
is
too large the resulting voltage drop can trigger the UVLO comparator. A recommended 1 μF capacitor coupled
with a 1Ω resistor provides approximately 10 dB of attenuation at 500 kHz switching frequency.
SWITCHING FREQUENCY SELECTION
The LM21305 supports a wide range of switching frequencies: 300 kHz to 1.5 MHz. The choice of switching
frequency is usually a compromise between conversion efficiency and the size of the circuit. Lower switching
frequency implies reduced switching losses (including gate charge losses, switch transition losses, etc.) and
usually results in higher overall efficiency. But higher switching frequency allows use of smaller LC output filters
and hence a more compact design. Lower inductance also helps transient response (higher large-signal slew
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