Datasheet

T
ON-MIN
D
MIN
= f
S
x
LM21305
www.ti.com SNVS639F –DECEMBER 2009–REVISED MARCH 2013
events, while at the same time providing frequency and voltage foldback protection during hard short circuit
conditions. The low-side switch also has negative current limit (-4.1A typical) for secondary protection, and this
can engage duing response to over-voltage events. If the negative current limit is triggered, the low-side switch
will be turned off. The negative current will be forced to go through the high-side switch body diode and will
quickly reduce.
PGOOD AND OVER- / UNDER-VOLTAGE HANDLING
PGOOD should be pulled high with an external resistor (10kΩ to 100kΩ recommended). When the FB voltage is
typically within -7% to +9.5% of the reference voltage, PGOOD will be high. Otherwise, an internal open-drain
pull-down device will pull PGOOD low. PGOOD should be tied to ground if the function is not required.
The LM21305 has built-in under- and over-voltage comparators that control the power switches. Whenever there
is an excursion in output voltage above the set OVP threshold, the device will terminate the present on-pulse,
turn on the low-side FET, and pull PGOOD low. The low-side FET will remain on until either the FB voltage falls
back into regulation or the inductor current zero-cross is detected which in turn tri-states the FETs. If the output
reaches the UVP threshold, the part will continue switching and PGOOD will be asserted and go low. To avoid
false tripping during transient glitches, PGOOD has 16 μs of built-in deglitch time to both rising and falling edges.
OVP is disabled during soft-start to prevent false triggering.
UVLO
The LM21305 has a built-in under-voltage lockout (UVLO) protection circuit that prevents the device from
switching until the AVIN voltage reaches 2.93V (typical). The UVLO threshold has typically 190 mV of hysteresis
that keeps the device from responding to power-on glitches during startup.
INTERNAL REGULATORS
The LM21305 contains two internal low dropout (LDO) regulators to produce internal driving and bias voltage
rails from AVIN. One LDO produces 5V to power the internal MOSFET drivers, the other produces 2.5V to power
the internal bias circuitry. Both the 5V0 or 2V5 LDOs should be bypassed to analog ground (AGND) with an
external ceramic capacitor (1 μF and 0.1 μF recommended, respectively). Good bypassing is necessary to
supply the high transient currents required by the power MOSFET gate drivers. Applications with high input
voltage and high switching frequency will increase die temperature because of the higher power dissipation
within the LDOs. Connecting a load to the 5V0 or 2V5 pins is not recommended since it will degrade their driving
capability to internal circuitry, further pushing the LDOs into their RMS current ratings and increasing power
dissipation and die temperature.
The LM21305 allows AVIN to be as low as 3V which makes the voltage at the 5V0 LDO lower than 5V. Low
supply voltage at the MOSFET drivers can increase on-time resistance of the high-side and low-side MOSFETs
and reduce efficiency of the regulator. When AVIN is between 3V and 5.5V, the best practice is to short the 5V0
pin to AVIN to avoid the voltage drop on the internal LDO. However, the device can be damaged if the 5V0 pin is
pulled to a voltage higher than 5.5V. For efficiency considerations, it is best to use AVIN = 5V if possible. When
AVIN is above 5V, reduced efficiency can be observed at light load due to the power loss of the LDOs. When
AVIN is close to 3V, increased MOSFET on-state resistance can reduce efficiency at high load current levels.
MINIMUM ON-TIME CONSIDERATIONS
Minimum on-time, T
ON-MIN
, is the smallest duration of time that the high-side MOSFET can be on. This time is
typically 70 ns in the LM21305. In CCM operation, the minimum on-time limit imposes a minimum duty cycle of
(4)
For a given output voltage, minimum on-time imposes limits on the switching regulator when operating
simultaneously at high input voltage and high switching frequency. As the equation shows, reducing the
operating frequency will alleviate the minimum duty cycle constraint. With a given switching frequency and
desired output voltage, the maximum allowed PVIN can be approximated by
Copyright © 2009–2013, Texas Instruments Incorporated Submit Documentation Feedback 13
Product Folder Links: LM21305