Datasheet

ManualsBrandsTEXAS INSTRUMENTS ManualsPMICsPMIC - DC/DC voltage regulator Holder WQFN 28

0.6V - 5V

VIN

LM21305

COMP

FREQ

PGOOD

PGND

2V5

AVIN

AGND

5V0

CBOOT

PVIN

5V0

2V5

FRQ

FB1

FB2

BOOT

OUT

SYNC

VOUT

EN1

EN2

LM21305

www.ti.com

SNVS639F –DECEMBER 2009–REVISED MARCH 2013

5A Adjustable Frequency Synchronous Buck Regulator

Check for Samples: LM21305

FEATURES

APPLICATIONS

• High Efficiency Switcher Core With Integrated

• POL Regulation From 3.3V, 5V, and 12V

Low R

DSon

Power MOSFETs Supply Rails

• Resistor Programmable Switching Frequency • High Efficiency Supply for DSPs, FPGAs,

With Frequency Synchronization ASICs and Processors

• Internal Soft-Start With Monotonic and Pre- • Broadband, Networking and Optical

Biased Startup Communications Infrastructure

• Low Shutdown Quiescent Current

DESCRIPTION

• Precision Enable With Hysteresis

The LM21305 is a full-featured 5A synchronous buck

• PGOOD Indicator Function

POL regulator optimized for solution size, flexibilty,

• Input Under-Voltage Lock-Out (UVLO)

and high conversion efficiency. High power density

LM21305 designs are achieved via monolithic

• Output Over-Voltage Protection (OVP)

integration of the high-side and low-side power

• High-Bandwidth Load Transient Response

MOSFETs, high switching frequency, current-mode

With Peak Current-Mode Control

control, and optimized thermal design. The efficiency

• Cycle-by-Cycle Current Limiting

of the LM21305 is elevated at light loads with diode

emulation mode operation and at heavy loads by

• Thermal Shutdown

optimal design of the MOSFET gate drivers to

minimize switch dead-times and body-diode

KEY SPECIFICATIONS

conduction losses.

• 3V to 18V Single-Rail Input Voltage

The LM21305 accepts a wide input voltage range of

• 0.598V Feedback Voltage Reference

3V to 18V, facilitating interface to all intermediate bus

• 300 kHz to 1.5 MHz Switching Frequency

voltages, including 3.3V, 5V and 12V rails. An output

voltage as low as 0.598V is supported with excellent

• WQFN-28 Package (5 x 5 x 0.8 mm, 0.5 mm

setpoint accuracy and low ripple and RMS noise.

Pitch)

Typical Application Circuit

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

2All trademarks are the property of their respective owners.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

Summary of content (33 pages)

PAGE 1
LM21305 www.ti.
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LM21305 SNVS639F – DECEMBER 2009 – REVISED MARCH 2013 www.ti.com DESCRIPTION (CONTINUED) The LM21305 offers flexible system configuration with programmable switching frequency from 300 kHz to 1.5 MHz using one resistor or via external clock synchronization. On-chip bias supply sub-regulators alleviate the need for external bias power and simplify PCB layout.
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LM21305 www.ti.com SNVS639F – DECEMBER 2009 – REVISED MARCH 2013 PIN DESCRIPTIONS Number Name Type (1) 1,2,27,28 PVIN P Input voltage to the power switches inside the device. 3,4,5,6 SW P Switch node output of the power switches. Voltage swings from PVIN to GND on this pin. SW also delivers current to the external inductor. 7,8,9,10 PGND G Power ground for the internal power switches. Compensation pin to connect to external compensation network.
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LM21305 SNVS639F – DECEMBER 2009 – REVISED MARCH 2013 www.ti.com ESD Ratings All pins, Human Body Model (1) (1) ±2kV The Human Body Model is a 100 pF capacitor discharged through a 1.5 kΩ resistor into each pin (MIL-STD-883 3015.7). Operating Ratings PVIN to PGND, AGND 3V to 18V AVIN to PGND, AGND 3V to 18V −40°C to 125°C Junction Temperature Ambient Temperature (1) −40°C to 85°C Junction-to-Ambient Thermal Resistance θJA (2) (1) (2) 32.
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LM21305 www.ti.com SNVS639F – DECEMBER 2009 – REVISED MARCH 2013 Electrical Characteristics (1) (2)(2) (continued) Specifications with standard typeface are for TJ = 25°C, and those in boldface type apply over the full Operating Temperature Range (TJ = -40°C to +125°C). Unless otherwise specified, VIN = VPVIN = VAVIN = 12V, VOUT = 3.3V, IOUT = 0A. Min Typ Max Unit VUVLO-HI-AVIN Symbol AVIN UVLO Rising Threshold Parameter Remarks 2.84 2.93 2.987 V VUVLO-LO-AVIN AVIN UVLO Falling Threshold 2.
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LM21305 SNVS639F – DECEMBER 2009 – REVISED MARCH 2013 www.ti.com Typical Performance Characteristics Unless otherwise specified: VIN = 12V, VOUT = 3.3V, fS = 500 kHz, TA = 25°C, L = 3.3 µH, COUT = 100 µF ceramic. Efficiency with PVIN = AVIN = 12V, fS = 300 kHz 100 100 95 95 90 90 EFFICIENCY (%) EFFICIENCY (%) Efficiency with PVIN = AVIN = 5V, fS = 300 kHz 85 80 75 70 65 85 80 75 70 65 VOUT = 3.3V VOUT = 1.8V VOUT = 1.2V VOUT = 0.
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LM21305 www.ti.com SNVS639F – DECEMBER 2009 – REVISED MARCH 2013 Typical Performance Characteristics (continued) Unless otherwise specified: VIN = 12V, VOUT = 3.3V, fS = 500 kHz, TA = 25°C, L = 3.3 µH, COUT = 100 µF ceramic. Load Regulation (%) Line Regulation (%) 0.10 LINE REGULATION (%) LOAD REGULATION (%) 0.10 0.05 0.00 -0.05 -0.10 0.05 0.00 -0.05 -0.10 0 1 2 3 4 LOAD CURRENT (A) 5 3 6 9 12 15 INPUT VOLTAGE, PVIN (V) Figure 8. Figure 9. VOUT Regulation (%) vs.
PAGE 8
LM21305 SNVS639F – DECEMBER 2009 – REVISED MARCH 2013 www.ti.com Typical Performance Characteristics (continued) Unless otherwise specified: VIN = 12V, VOUT = 3.3V, fS = 500 kHz, TA = 25°C, L = 3.3 µH, COUT = 100 µF ceramic. Soft-Start, No Load Soft-Start with Resistive Load IOUT 1A/DIV EN 1V/DIV VOUT 1V/DIV PGOOD 1V/DIV PGOOD 1V/DIV EN 1V/DIV VOUT 1V/DIV IOUT 1A/DIV 2 ms/DIV 2 ms/DIV Figure 14. Figure 15.
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LM21305 www.ti.com SNVS639F – DECEMBER 2009 – REVISED MARCH 2013 BLOCK DIAGRAM C7 R1 C6 C5 AVIN 2V5 CBOOT 5V0 VIN LDO1 5V LDO2 2.5V PVIN C1 OTP ISENSE UVLO HS FET OCP C2 SS Nonoverlap EN + L1 VOUT EA REF PWM PWM Control Logic 1.2V PGOOD Slope Comp Input UVLO Output UV, OV AGND OVP SW Z cross LS FET OCP Rev OCP OTP C3 Nonoverlap FB OSC/ Sync COMP FREQ SYNC PGND R1 C5 R4 C4 OPERATION DESCRIPTION The LM21305 employs peak current-mode control. The 0.
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LM21305 SNVS639F – DECEMBER 2009 – REVISED MARCH 2013 www.ti.com PEAK CURRENT-MODE CONTROL In most applications, the peak current-mode control architecture used in the LM21305 only requires two external components to achieve a stable design. External compensation allows the user to set the crossover frequency and phase margin, thus optimizing the transient performance of the device.
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LM21305 www.ti.com IBOUNDARY = SNVS639F – DECEMBER 2009 – REVISED MARCH 2013 VOUT (1 -D) 2LfS (1) Switchnode Voltage where D is the duty cycle of the high-side switch, equal to the high-side switch on-time divided by the switching period. For more details, please refer to the CALCULATING THE DUTY CYCLE section in the Design Guide provided later. Several diagrams are shown in Figure 22 illustrating continuous conduction mode (CCM), Discontinuous Conduction Mode (DCM), and the boundary condition.
PAGE 12
LM21305 SNVS639F – DECEMBER 2009 – REVISED MARCH 2013 www.ti.com PRECISION ENABLE The enable (EN) pin allows the output of the device to be enabled or disabled with an external control signal. This pin is a precision analog input that enables the device when the voltage exceeds 1.2V (typical). The EN pin has 200 mV (typical) of hysteresis and will disable the output when the enable voltage falls below 1.0V (typical). If the EN pin is not used, it should be pulled up to AVIN via a 10 kΩ to 100 kΩ resistor.
PAGE 13
LM21305 www.ti.com SNVS639F – DECEMBER 2009 – REVISED MARCH 2013 events, while at the same time providing frequency and voltage foldback protection during hard short circuit conditions. The low-side switch also has negative current limit (-4.1A typical) for secondary protection, and this can engage duing response to over-voltage events. If the negative current limit is triggered, the low-side switch will be turned off.
PAGE 14
LM21305 SNVS639F – DECEMBER 2009 – REVISED MARCH 2013 VPVIN-max = www.ti.com 1 VOUT x fS TON-MIN (5) Similarly, if the PVIN input rail is fixed, the maximum switching frequency without imposing minimum on-time can be found by: fs-max = 1 VOUT x VPVIN-max TON-MIN (6) In rare cases where steady-state operation at minimum duty cycle is unavoidable, the regulator will automatically skip cycles to keep VOUT regulated, similar to light-load DCM operation.
PAGE 15
LM21305 www.ti.com SNVS639F – DECEMBER 2009 – REVISED MARCH 2013 DESIGN GUIDE This section walks the designer through the steps necessary to select the external components to build a fully functional efficient step-down power supply. As with any DC-DC converter, numerous tradeoffs are possible to optimize the design for efficiency, size, and performance. These will be taken into account and highlighted throughout this discussion.
PAGE 16
LM21305 SNVS639F – DECEMBER 2009 – REVISED MARCH 2013 www.ti.com CALCULATING THE DUTY CYCLE The first equation to calculate for any buck converter is duty cycle. In an ideal (no loss) buck converter, the duty cycle can be found by: § VOUT ©VPVIN § © Dideal = (8) In applications with low output voltage (<1.2V) and high load current (> 3A), the losses should not be ignored when calculation the duty cycle.
PAGE 17
LM21305 www.ti.com SNVS639F – DECEMBER 2009 – REVISED MARCH 2013 rate of inductor current) and reduces the DCR losses. The optimal switching frequency is usually a tradeoff in a given application and thus needs to be determined on a case-by-case basis. It is related to the input voltage, output voltage, most common load current level, external component choices, and circuit size requirements. The choice of switching frequency may also be limited if an operating condition triggers TON-MIN or TOFF-MIN.
PAGE 18
LM21305 SNVS639F – DECEMBER 2009 – REVISED MARCH 2013 www.ti.com Once the inductance is determined, the type of inductor must be selected. Ferrite designs have very low core losses and are preferred at high switching frequencies, so design goals can concentrate on copper loss and preventing saturation. Ferrite core material saturates hard, which means that inductance collapses abruptly when the saturation current is exceeded.
PAGE 19
LM21305 www.ti.com SNVS639F – DECEMBER 2009 – REVISED MARCH 2013 One or more ceramic capacitors are generally recommended because they have very low ESR and remain capacitive up to high frequencies. The capacitor dielectric should be X5R or X7R to maintain proper tolerance. Other types of capacitors also can be used, particularly if large bulk capacitance is needed (such as tantalum, POSCAP and OSCON). Such electrolytic capacitors have lower ESR zero {1/(2πESR *COUT} frequency than ceramic capacitors.
PAGE 20
LM21305 SNVS639F – DECEMBER 2009 – REVISED MARCH 2013 www.ti.com IOUT-MAX 5.0A 2.5A 0 50% 100% D Figure 28. LM21305 Maximum Load Current Derating when D > 50% CONTROL LOOP COMPENSATION VREF + VOUT(s) VC(s) + Compensator Fcomp(s) - Fp(s) x Fh(s) Power Stage Loop T(s) H(s) Feedback Figure 29.
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LM21305 www.ti.com SNVS639F – DECEMBER 2009 – REVISED MARCH 2013 Gain0/sCc1 fp fzcomp fc 0 dB fs/2 fESR (fpcomp) Figure 31. LM21305 Loop Gain Asymptotic Approximation The loop gain determines both static and dynamic performance of the converter. The power stage response is fixed by the selection of the power components and the compensator is therefore designed around the power stage response to achieve the desired loop response.
PAGE 22
LM21305 SNVS639F – DECEMBER 2009 – REVISED MARCH 2013 Fh (s) = www.ti.com 1 s2 s + 1+ wn Qp wn2 (26) where: wn = Sfs and Qp = 1 S(mcD' ± 0.5) (27) The compensator network transfer function is: (28) With the above equations, the loop gain T(s) can be plotted and more accurate loop performance metrics (crossover frequency and phase margin) can be determined.
PAGE 23
LM21305 www.ti.com SNVS639F – DECEMBER 2009 – REVISED MARCH 2013 PCB LAYOUT CONSIDERATIONS PC board layout is an important and critical part of any DC-DC converter design. Poor PC board layout can disrupt the performance of a DC-DC converter and surrounding circuitry by contributing to EMI, ground bounce, resistive voltage loss in the traces, and thermal problems. Erroneous signals can reach the DC-DC converter, possibly resulting in poor regulation or instability.
PAGE 24
LM21305 SNVS639F – DECEMBER 2009 – REVISED MARCH 2013 IOUT = Output (load) current Rdcr = Inductor parasitic DC resistance www.ti.com It is important to always keep the LM21305 operating junction temperature (TJ) below 125°C to assure reliable operation. If the junction temperature exceeds 160°C, the device will cycle in and out of thermal shutdown. If thermal shutdown occurs, it is a sign of inadequate heat-sinking and/or excessive power dissipation in the device.
PAGE 25
LM21305 www.ti.com SNVS639F – DECEMBER 2009 – REVISED MARCH 2013 Application Circuit Example VIN = 12V PVIN CIN1 CIN2 CBOOT CBOOT CIN3 VOUT L SW RF AVIN REN RFB1 CF LM21305 EN RFB2 Rc Cc 2V5 COMP C2V5 RPG COUT1 COUT2 FB 5V0 C5V0 CFRQ FREQ PGOOD AGND PGND RFRQ Figure 32. LM21305 Application Circuit Example Table 1. Bill Of Materials (500kHz Switching Frequency) VOUT 1.2V 1.8V 2.5V 3.
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LM21305 SNVS639F – DECEMBER 2009 – REVISED MARCH 2013 www.ti.com PCB Layout Figure 33. PCB Top Layer Copper and Silkscreen An example of an LM21305 PCB layout is shown in Figure 33. Only the top layer copper and top silkscreen are shown. For more details, please refer to Application Note AN-2042 (literature number SNVA432).
PAGE 27
LM21305 www.ti.com SNVS639F – DECEMBER 2009 – REVISED MARCH 2013 REVISION HISTORY Changes from Revision E (March 2013) to Revision F • Page Changed layout of National Data Sheet to TI format ..........................................................................................................
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PACKAGE OPTION ADDENDUM www.ti.
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PACKAGE OPTION ADDENDUM www.ti.com 18-Oct-2013 continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
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PACKAGE MATERIALS INFORMATION www.ti.com 8-Apr-2013 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing LM21305SQ/NOPB WQFN RSG 28 LM21305SQE/NOPB WQFN RSG LM21305SQX/NOPB WQFN RSG SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant 1000 178.0 12.4 5.3 5.3 1.3 8.0 12.0 Q1 28 250 178.0 12.4 5.3 5.3 1.3 8.0 12.0 Q1 28 4500 330.0 12.4 5.3 5.3 1.3 8.0 12.
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PACKAGE MATERIALS INFORMATION www.ti.com 8-Apr-2013 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) LM21305SQ/NOPB WQFN RSG 28 1000 213.0 191.0 55.0 LM21305SQE/NOPB WQFN RSG 28 250 213.0 191.0 55.0 LM21305SQX/NOPB WQFN RSG 28 4500 367.0 367.0 35.
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MECHANICAL DATA RSG0028B TOP SIDE OF PACKAGE BOTTOM SIDE OF PACKAGE SQA28B (Rev A) www.ti.
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