Datasheet

f
S
x 0.4 x I
L(MAX)
(1 ± D)
x V
OUT
f
S
x 0.2 x I
L(MAX)
(1 ± D)
x V
OUT
7 L 7
'i
Lp-p
=
f
S
x L
(1 - D)
x V
OUT
1
T
ON-MIN
x
V
OUT
V
PVIN-max
=
f
s-max
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where, R
ESR_CIN
is the ESR of the input capacitor. This equation has a maximum at PVIN = 2V
OUT
, where
I
RMS
≅ I
OUT
/2. This simple worst-case condition is commonly used for design because even significant
deviations do not offer much relief. Several capacitors may also be paralleled to meet size or height
requirements in the design. For low input voltage applications, sufficient bulk input capacitance is needed
to minimize transient effects during load current changes. For optimal high frequency decoupling, a 1 µF
ceramic bypass capacitor is also recommended adjacent the IC between the PVIN and PGND pins.
Please refer to the PCB layout recommendation section in the LM21305 datasheet for more details. Note
that the ESR of an electrolytic capacitor is used in this eval board to damp any oscillations that may occur
when the supply lines have parasitic series inductance.
9.2 AVIN Filter
This can be seen on the schematic as components R
F
and C
F
. There is a practical limit to the size of the
resistor R
F
as the AVIN pin will draw a short 60mA burst of current during startup, and if R
F
is too large the
resulting voltage drop can trigger the UVLO comparator. For the evaluation board, a 1Ω resistor is used
for R
F
ensuring that the UVLO will not be triggered after the part is enabled. A recommended 1 μF C
F
capacitor coupled with the 1Ω resistor provides approximately 10 dB of attenuation at 500 kHz switching
frequency.
9.3 Switching Frequency Selection
The LM21305 supports a wide range of switching frequencies: 300 kHz to 1.5 MHz. The choice of
switching frequency is usually a compromise between efficiency and size of the circuit. Lower switching
frequency usually implies lower switching losses (including gate charge losses, transition losses, etc.) and
would typically result in a better efficiency. But higher switching frequency allows the use of smaller LC
filters to achieve a more compact design. Lower inductance also helps transient response (faster large-
signal slew rate of inductor current) and reduces the conduction loss associated with the inductor DCR.
The optimal switching frequency for efficiency needs to be determined on a case by case basis. It is
related to the input voltage, the output voltage, the most frequent load level, external component choices,
and circuit size requirement. The choice of switching frequency is also limited if an operating condition is
possible to trigger T
ON-MIN
and T
OFF-MIN
. The maximum frequency that can be used for a given input and
output voltage can be found by:
(2)
The following equation should be used to calculate resistor R4 value in order to obtain a desired frequency
of operation:
f
s
[kHz] = 31000 * R
−0.9
[kΩ]
9.4 Inductor
A general recommendation for the inductor in the LM21305 application is to keep the peak-to-peak ripple
current between 20% and 40% of the maximum DC load current (5A), 30% is desired. The inductor also
should have a high enough current rating and a DCR as small as possible.
The peak-to-peak current ripple can be calculated by:
(3)
The current ripple is larger with smaller inductance and/or lower switching frequency. In general, with a
fixed output voltage, the higher the PVIN, the higher the inductor current ripple. If PVIN is kept constant,
inductor current ripple is highest at 50% duty cycle. It is recommended to choose L such that:
(4)
The inductor should be rated to handle the maximum load current plus the ripple current.
I
L(MAX)
= I
LOAD(MAX)
+ Δi
L(MAX)
/2
8
AN-2042 LM21305 Evaluation Board SNVA432C–March 2010–Revised May 2013
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