Datasheet

PVIN
SW
PGND
L
V
OUT
LM21215
C
IN
C
OUT
LOOP1
LOOP2
V
IN
LM21215
www.ti.com SNVS625E –FEBRUARY 2011–REVISED MARCH 2013
6. Provide adequate device heatsinking. For most 15A designs a four layer board is recommended. Use as many
vias as is possible to connect the EP to the power plane heatsink. The vias located undernieth the EP will wick
solder into them if they are not filled. Complete solder coverage of the EP to the board is required to achieve the
θ
JA
values described in the previous section. Either an adequate amount of solder must be applied to the EP pad
to fill the vias, or the vias must be filled during manufacturing. See the THERMAL CONSIDERATIONS section to
ensure enough copper heatsinking area is used to keep the junction temperature below 125°C.
Figure 38. Schematic of LM21215 Highlighting Layout Sensitive Nodes
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