Datasheet

10 100 1k 10k 100k 1M
-50
0
50
100
150
200
-40
-20
0
20
40
60
80
100
120
140
160
GAIN (dB)
FREQUENCY (Hz)
PHASE MARGIN (°)
GAIN
PHASE
1
2Sf
ESR
R
C2
C
C3
=
= 898 pF
f
LC
f
ESR
- f
LC
R
C2
=
R
FB1
= 166:
C
C2
=
C
C1
Sf
SW
R
C1
C
C1
-1
= 71 pF
1
C
C1
=
Sf
LC
R
C1
= 1.99 nF
R
C1
=
f
crossover
f
LC
'V
RAMP
V
IN
R
FB1
=
100 kHz
17.4 kHz
10 k:
0.8 V
5.0 V
=
9.2 k:
LM21215
SNVS625E –FEBRUARY 2011–REVISED MARCH 2013 www.ti.com
accurately calculate the compensation network. The example given here is the total output capacitance using the
three MLCC output capacitors biased at 1.2V, as seen in the typical application schematic, Figure 39. Note that it
is more conservative, from a stability standpoint, to err on the side of a smaller output capacitance value in the
compensation calculations rather than a larger, as this will result in a lower bandwidth but increased phase
margin.
First, a the value of R
FB1
should be chosen. A typical value is 10 kΩ. From this, the value of R
C1
can be
calculated to set the mid-band gain so that the desired crossover frequency is achieved:
(17)
Next, the value of C
C1
can be calculated by placing a zero at half of the LC double pole frequency (f
LC
):
(18)
Now the value of C
C2
can be calculated to place a pole at half of the switching frequency (f
SW
):
(19)
R
C2
can then be calculated to set the second zero at the LC double pole frequency:
(20)
Last, C
C3
can be calculated to place a pole at the same frequency as the zero created by the output capacitor
ESR:
(21)
An illustration of the total loop response can be seen in Figure 35.
Figure 35. Loop Response
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