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f
Z2
= f
LC
=
f
P1
= f
ESR
=
2
f
P2
=
f
sw
f
Z1
=
f
LC
2
1
2SR
C1
C
C1
=
1
2S(R
C1
+ R
FB1
)C
C3
C
C1
+
C
C2
2SR
C1
C
C1
C
C2
1
2SR
C2
C
C3
=
100 1k 10k 100k 1M 10M
-20
0
20
40
60
80
100
-180
-135
-90
-45
0
45
90
GAIN (dB)
FREQUENCY (Hz)
PHASE (°)
GAIN
PHASE
LM21215
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SNVS625E –FEBRUARY 2011–REVISED MARCH 2013
Figure 34. Type 3 Compensation Network Bode Plot
As seen in Figure 34, the two zeros (f
LC
/2, f
LC
) in the comensation network give a phase boost. This will cancel
out the effects of the phase loss from the output filter. The compensation network also adds two poles to the
system. One pole should be located at the zero caused by the output capacitor ESR (f
ESR
) and the other pole
should be at half the switching frequency (f
SW
/2) to roll off the high frequency response. The dependancy of the
pole and zero locations on the compensation components is described below.
(16)
An example of the step-by-step procedure to generate comensation component values using the typical
application setup, (see Figure 39), is given. The parameters needed for the compensation values are given in the
table below.
Parameter Value
V
IN
5.0V
V
OUT
1.2V
I
OUT
15A
f
CROSSOVER
100 kHz
L 0.56 µH
R
DCR
1.8 mΩ
C
O
150 µF
R
ESR
1.0 mΩ
ΔV
RAMP
0.8V
f
SW
500 kHz
where ΔV
RAMP
is the oscillator peak-to-peak ramp voltage (nominally 0.8V), and f
CROSSOVER
is the frequency at
which the open-loop gain is a magnitude of 1. It is recommended that the f
CROSSOVER
not exceed one-fifth of the
switching frequency. The output capacitance, C
O
, depends on capacitor chemistry and bias voltage. For Multi-
Layer Ceramic Capacitors (MLCC), the total capacitance will degrade as the DC bias voltage is increased.
Measuring the actual capacitance value for the output capacitors at the output voltage is recommended to
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