Datasheet

P
D
= P
IN
(1 - Efficiency) - I
OUT
2
R
DCR
T
J
= P
D
T
JA
+ T
A
10 100 1k 10k 100k 1M
-50
0
50
100
150
200
-40
-20
0
20
40
60
80
100
120
140
160
GAIN (dB)
FREQUENCY (Hz)
PHASE MARGIN (°)
GAIN
PHASE
LM21212-2
www.ti.com
SNVS715A MARCH 2011REVISED MARCH 2013
Figure 33. Loop Response
It is important to verify the stability by either observing the load transient response or by using a network
analyzer. A phase margin between 45° and 70° is usually desired for voltage mode systems. Excessive phase
margin can cause slow system response to load transients and low phase margin may cause an oscillatory load
transient response. If the load step response peak deviation is larger than desired, increasing f
CROSSOVER
and
recalculating the compensation components may help but usually at the expense of phase margin.
THERMAL CONSIDERATIONS
The thermal characteristics of the LM21212-2 are specified using the parameter θ
JA
, which relates the junction
temperature to the ambient temperature. Although the value of θ
JA
is dependant on many variables, it still can be
used to approximate the operating junction temperature of the device.
To obtain an estimate of the device junction temperature, one may use the following relationship:
(20)
and
(21)
Where:
T
J
is the junction temperature in °C, P
IN
is the input power in Watts (P
IN
= V
IN
x I
IN
), θ
JA
is the junction to ambient
thermal resistance for the LM21212-2, T
A
is the ambient temperature in °C, and I
OUT
is the output load current in
A.
It is important to always keep the operating junction temperature (T
J
) below 125°C for reliable operation. If the
junction temperature exceeds 165°C the device will cycle in and out of thermal shutdown. If thermal shutdown
occurs it is a sign of inadequate heatsinking or excessive power dissipation in the device.
Figure 34, shown below, provides a better approximation of the θ
JA
for a given PCB copper area. The PCB used
in this test consisted of 4 layers: 1oz. copper was used for the internal layers while the external layers were
plated to 2oz. copper weight. To provide an optimal thermal connection, a 3 x 4 array of 8 mil. vias under the
thermal pad were used, and an additional sixteen 8 mil. vias under the rest of the device were used to connect
the 4 layers.
Copyright © 2011–2013, Texas Instruments Incorporated Submit Documentation Feedback 21
Product Folder Links: LM21212-2