Datasheet
f
Z2
= f
LC
=
f
P1
= f
ESR
=
2
f
P2
=
f
sw
f
Z1
=
f
LC
2
1
2SR
C1
C
C1
=
1
2S(R
C1
+ R
FB1
)C
C3
C
C1
+
C
C2
2SR
C1
C
C1
C
C2
1
2SR
C2
C
C3
=
100 1k 10k 100k 1M 10M
-20
0
20
40
60
80
100
-180
-135
-90
-45
0
45
90
GAIN (dB)
FREQUENCY (Hz)
PHASE (°)
GAIN
PHASE
LM21212-2
www.ti.com
SNVS715A –MARCH 2011–REVISED MARCH 2013
The pole located at the origin gives high open loop gain at DC, translating into improved load regulation
accuracy. This pole occurs at a very low frequency due to the limited gain of the error amplifier; however, it can
be approximated at DC for the purposes of compensation. The other two poles and two zeros can be located
accordingly to stabilize the voltage mode loop depending on the power stage complex poles and Q. Figure 32 is
an illustration of what the Error Amplifier Compensation transfer function will look like.
Figure 32. Type 3 Compensation Network Bode Plot
As seen in Figure 32, the two zeros (f
LC
/2, f
LC
) in the comensation network give a phase boost. This will cancel
out the effects of the phase loss from the output filter. The compensation network also adds two poles to the
system. One pole should be located at the zero caused by the output capacitor ESR (f
ESR
) and the other pole
should be at half the switching frequency (f
SW
/2) to roll off the high frequency response. The dependancy of the
pole and zero locations on the compensation components is described below.
(14)
An example of the step-by-step procedure to generate compensation component values using the typical
application setup (see Figure 37) is given. The parameters needed for the compensation values are given in the
table below.
Parameter Value
V
IN
5.0V
V
OUT
1.2V
I
OUT
12A
f
CROSSOVER
100 kHz
L 0.56 µH
R
DCR
1.8 mΩ
C
O
150 µF
R
ESR
1.0 mΩ
ΔV
RAMP
0.8V
f
SW
500 kHz
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