Datasheet

LM21212-1
SNVS671E –FEBRUARY 2011–REVISED MARCH 2013 www.ti.com
UVLO
The LM21212-1 has a built-in under-voltage lockout protection circuit that keeps the device from switching until
the input voltage reaches 2.7V (typical). The UVLO threshold has 200 mV of hysteresis that keeps the device
from responding to power-on glitches during start up. If desired the turn-on point of the supply can be changed
by using the precision enable pin and a resistor divider network connected to VIN as shown in Figure 30 in the
design guide.
CURRENT LIMIT
The LM21212-1 has current limit protection to avoid dangerous current levels on the power FETs and inductor. A
current limit condition is met when the current through the high side FET exceeds the rising current limit level
(I
CLR
). The control circuitry will respond to this event by turning off the high side FET and turning on the low side
FET. This forces a negative voltage on the inductor, thereby causing the inductor current to decrease. The high
side FET will not conduct again until the lower current limit level (I
CLF
) is sensed on the low side FET. At this
point, the device will resume normal switching.
A current limit condition will cause the internal soft-start voltage to ramp downward. After the internal soft-start
ramps below the Feedback (FB) pin voltage, (nominally 0.6 V), FB will begin to ramp downward, as well. This
voltage foldback will limit the power consumption in the device, thereby protecting the device from continuously
supplying power to the load under a condition that does not fall within the device SOA. After the current limit
condition is cleared, the internal soft-start voltage will ramp up again. Figure 26 shows current limit behavior with
V
SS
, V
FB
, V
OUT
and V
SW
.
SHORT-CIRCUIT PROTECTION
In the unfortunate event that the output is shorted with a low impedance to ground, the LM21212-1 will limit the
current into the short by resetting the device. A short-circuit condition is sensed by a current-limit condition
coinciding with a voltage on the FB pin that is lower than 100 mV. When this condition occurs, the device will
begin its reset sequence, turning off both power FETs and discharging the soft-start capacitor after t
RESETSS
(nominally 110 µs). The device will then attempt to restart. If the short-circuit condition still exists, it will reset
again, and repeat until the short-circuit is cleared. The reset prevents excess current flowing through the FETs in
a highly inefficient manner, potentially causing thermal damage to the device or the bus supply.
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