Datasheet

LM20333

www.ti.com

SNVS558D –MAY 2008–REVISED APRIL 2013

Figure 36, shown below, provides a better approximation of the θ

for a given PCB copper area. The PCB used

in this test consisted of 4 layers: 1oz. copper was used for the internal layers while the external layers were

plated to 2oz. copper weight. To provide an optimal thermal connection, a 5 x 4 array of 12 mil thermal vias

located under the thermal pad was used to connect the 4 layers.

Figure 36. Thermal Resistance vs PCB Area (4 Layer Board)

PCB LAYOUT CONSIDERATIONS

PC board layout is an important part of DC-DC converter design. Poor board layout can disrupt the performance

of a DC-DC converter and surrounding circuitry by contributing to EMI, ground bounce, and resistive voltage loss

in the traces. These can send erroneous signals to the DC-DC converter resulting in poor regulation or instability.

Good layout can be implemented by following a few simple design rules.

1. Minimize area of switched current loops. In a buck regulator there are two loops where currents are switched

at high slew rates. The first loop starts from the input capacitor, to the regulator VIN pin, to the regulator SW pin,

to the inductor then out to the output capacitor and load. The second loop starts from the output capacitor

ground, to the regulator GND pins, to the inductor and then out to the load (see Figure 37). To minimize both

loop areas the input capacitor should be placed as close as possible to the VIN pin. Grounding for both the input

and output capacitor should consist of a small localized top side plane that connects to GND and the exposed

pad (EP). The inductor should be placed as close as possible to the SW pin and output capacitor.

2. Minimize the copper area of the switch node. Since the LM20333 has the SW pins on opposite sides of the

package it is recommended that the SW pins should be connected with a trace that runs around the package.

The inductor should be placed at an equal distance from the SW pins using 100 mil wide traces to minimize

capacitive and conductive losses.

3. Have a single point ground for all device grounds located under the EP. The ground connections for the

compensation, feedback, and soft-start components should be connected together then routed to the EP pin of

the device. The AGND pin should connect to GND under the EP. If not properly handled poor grounding can

result in degraded load regulation or erratic switching behavior.

4. Minimize trace length to the FB pin. Since the feedback node can be high impedance the trace from the output

resistor divider to FB pin should be as short as possible. This is most important when high value resistors are

used to set the output voltage. The feedback trace should be routed away from the SW pin and inductor to avoid

contaminating the feedback signal with switch noise.

5. Make input and output bus connections as wide as possible. This reduces any voltage drops on the input or

output of the converter and can improve efficiency. Voltage accuracy at the load is important so make sure

feedback voltage sense is made at the load. Doing so will correct for voltage drops at the load and provide the

best output accuracy.

6. Provide adequate device heatsinking. For most 3A designs a four layer board is recommended. Use as many

vias as is possible to connect the EP to the power plane heatsink. For best results use a 5x4 via array with a

minimum via diameter of 12 mils. "Via tenting" with the solder mask may be necessary to prevent wicking of the

solder paste applied to the EP. See the THERMAL CONSIDERATIONS section to ensure enough copper

heatsinking area is used to keep the junction temperature below 125°C.

Product Folder Links: LM20333