Datasheet

PVIN

PGND

OUT

LM20323

OUT

LOOP1

LOOP2

LM20323

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SNVS557C –MAY 2008–REVISED APRIL 2013

2. Minimize the copper area of the switch node. Since the LM20323 has the SW pins on opposite sides of the

package it is recommended that the SW pins should be connected with a trace that runs around the package.

The inductor should be placed at an equal distance from the SW pins using 100 mil wide traces to minimize

capacitive and conductive losses.

3. Have a single point ground for all device grounds located under the EP. The ground connections for the

compensation, feedback, and soft-start components should be connected together then routed to the EP pin of

the device. The AGND pin should connect to GND under the EP. If not properly handled poor grounding can

result in degraded load regulation or erratic switching behavior.

4. Minimize trace length to the FB pin. Since the feedback node can be high impedance the trace from the output

resistor divider to FB pin should be as short as possible. This is most important when high value resistors are

used to set the output voltage. The feedback trace should be routed away from the SW pin and inductor to avoid

contaminating the feedback signal with switch noise.

5. Make input and output bus connections as wide as possible. This reduces any voltage drops on the input or

output of the converter and can improve efficiency. Voltage accuracy at the load is important so make sure

feedback voltage sense is made at the load. Doing so will correct for voltage drops at the load and provide the

best output accuracy.

6. Provide adequate device heatsinking. For most 3A designs a four layer board is recommended. Use as many

vias as is possible to connect the EP to the power plane heatsink. For best results use a 5x4 via array with a

minimum via diameter of 12 mils. "Via tenting" with the solder mask may be necessary to prevent wicking of the

solder paste applied to the EP. See the THERMAL CONSIDERATIONS section to ensure enough copper

heatsinking area is used to keep the junction temperature below 125°C.

Figure 33. Schematic of LM20323 Highlighting Layout Sensitive Nodes

Product Folder Links: LM20323