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VIN

AGND

PGOOD

OUT

FB1

FB2

OUT

SS/TRK

VCC

COMP

LM20323

BOOT

GND

BOOT

(Optional)

LM20323

www.ti.com

SNVS557C –MAY 2008–REVISED APRIL 2013

LM20323 36V, 3A 500 kHz Synchronous Buck Regulator

Check for Samples: LM20323

FEATURES

APPLICATIONS

• 4.5V to 36V Input Voltage Range

• Simple to Design, high Efficiency Point of

Load Regulation from a 4.5V to 36V Bus

• 3A Output Current, 5.2A Peak Current

• High Performance DSPs, FPGAs, ASICs and

• 130 mΩ/110 mΩ Integrated Power MOSFETs

Microprocessors

• 93% Peak Efficiency with Synchronous

• Communications Infrastructure, Automotive

Rectification

DESCRIPTION

• 1.5% Feedback Voltage Accuracy

The LM20323 is a full featured 500kHz synchronous

• Current Mode Control, Selectable

buck regulator capable of delivering up to 3A of load

Compensation

current. The current mode control loop is externally

• Fixed 500 kHz Switching Frequency

compensated with only two components, offering both

high performance and ease of use. The device is

• Adjustable Output Voltage Down to 0.8V

optimized to work over the input voltage range of

• Compatible with Pre-biased Loads

4.5V to 36V making it well suited for high voltage

• Programmable Soft-start with External

systems.

Capacitor

The device features internal Over Voltage Protection

• Precision Enable Pin with Hysteresis

(OVP) and Over Current Protection (OCP) circuits for

increased system reliability. A precision Enable pin

• Integrated OVP, UVLO, PGOOD

and integrated UVLO allows the turn-on of the device

• Internally Protected with Peak Current Limit,

to be tightly controlled and sequenced. Startup inrush

Thermal Shutdown and Restart

currents are limited by both an internally fixed and

• Accurate Current Limit Minimizes Inductor

externally adjustable soft-start circuit. Fault detection

Size

and supply sequencing are possible with the

integrated power good (PGOOD) circuit.

• Non-linear Current Mode Slope Compensation

• 20-Pin HTSSOP Exposed Pad Package

Simplified Application Circuit

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

2All trademarks are the property of their respective owners.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

Summary of content (28 pages)

PAGE 1
LM20323 www.ti.com SNVS557C – MAY 2008 – REVISED APRIL 2013 LM20323 36V, 3A 500 kHz Synchronous Buck Regulator Check for Samples: LM20323 FEATURES APPLICATIONS • • • • • 1 2 • • • • • • • • • • • • 4.5V to 36V Input Voltage Range 3A Output Current, 5.2A Peak Current 130 mΩ/110 mΩ Integrated Power MOSFETs 93% Peak Efficiency with Synchronous Rectification 1.
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LM20323 SNVS557C – MAY 2008 – REVISED APRIL 2013 www.ti.com DESCRIPTION (CONTINUED) The LM20323 is designed to work well in multi-rail power supply architectures. The output voltage of the device can be configured to track a higher voltage rail using the SS/TRK pin. If the output of the LM20323 is pre-biased at startup it will not sink current to pull the output low until the internal soft-start ramp exceeds the voltage at the feedback pin.
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LM20323 www.ti.com SNVS557C – MAY 2008 – REVISED APRIL 2013 These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. Absolute Maximum Ratings (1) (2) VIN to GND -0.3V to +38V BOOT to GND -0.3V to +43V BOOT to SW -0.3V to +7V SW to GND -0.5V to +38V SW to GND (Transient) -1.5V (< 20 ns) FB, EN, SS/TRK, COMP, PGOOD to GND -0.
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LM20323 SNVS557C – MAY 2008 – REVISED APRIL 2013 www.ti.com Electrical Characteristics (continued) Unless otherwise stated, the following conditions apply: VVIN = 12V. Limits in standard type are for TJ = 25°C only, limits in bold face type apply over the junction temperature (TJ) range of -40°C to +125°C. Minimum and maximum limits are specified through test, design, or statistical correlation.
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LM20323 www.ti.com SNVS557C – MAY 2008 – REVISED APRIL 2013 Typical Performance Characteristics Unless otherwise specified: VVIN = 12V, VOUT = 3.3V, L= 5.6 µH, CSS = 100nF, TA = 25°C for efficiency curves, loop gain plots and waveforms, and TJ = 25°C for all others. Efficiency vs. Load Current Error Amplifier Gain Figure 2. Figure 3. Error Amplifier Phase Line Regulation Figure 4. Figure 5. Load Regulation VCC vs. VIN Figure 6. Figure 7.
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LM20323 SNVS557C – MAY 2008 – REVISED APRIL 2013 www.ti.com Typical Performance Characteristics (continued) Unless otherwise specified: VVIN = 12V, VOUT = 3.3V, L= 5.6 µH, CSS = 100nF, TA = 25°C for efficiency curves, loop gain plots and waveforms, and TJ = 25°C for all others. 6 Non-Switching IQ vs. VIN Shutdown IQ vs. VIN Figure 8. Figure 9. PGOOD Output Low Level Voltage vs. IPGOOD Enable Threshold and Hysteresis vs. Temperature Figure 10. Figure 11. UVLO Threshold and Hysteresis vs.
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LM20323 www.ti.com SNVS557C – MAY 2008 – REVISED APRIL 2013 Typical Performance Characteristics (continued) Unless otherwise specified: VVIN = 12V, VOUT = 3.3V, L= 5.6 µH, CSS = 100nF, TA = 25°C for efficiency curves, loop gain plots and waveforms, and TJ = 25°C for all others. Oscillator Frequency vs. VIN High-Side FET Resistance vs. Temperature Figure 14. Figure 15. Load Transient Response Low-Side FET Resistance vs. Temperature Figure 16. Figure 17. Peak Current Limit vs.
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LM20323 SNVS557C – MAY 2008 – REVISED APRIL 2013 www.ti.com Typical Performance Characteristics (continued) Unless otherwise specified: VVIN = 12V, VOUT = 3.3V, L= 5.6 µH, CSS = 100nF, TA = 25°C for efficiency curves, loop gain plots and waveforms, and TJ = 25°C for all others. Startup with CSS = 0 Startup with CSS = 100 nF Figure 20. Figure 21. Startup with Applied Track Signal Figure 22.
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LM20323 www.ti.com SNVS557C – MAY 2008 – REVISED APRIL 2013 Block Diagram VCC_INT BOOT INTERNAL +5.5V REGULATOR BOOT VCC ENABLE_INT VIN UVLO + - 4.25V +5.5V REGULATOR VCC 2.7V +2.7V REGULATOR SLOPE COMP COMP 2.7V CURRENT SENSE + 4.5 PA DISCHARGE ERROR AMP gm = 515 Pmho SS/TRK + FB DISCHARGE CURRENT LIMIT 5.2A VREF + 800 mV - BOOT + - + + PWM COMPARATOR 880 mV 740 mV + - PG-L + - VCC_INT NEGATIVE CURRENT LIMIT OVERVOLTAGE UNDERVOLTAGE + - CONTROL LOGIC -2.
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LM20323 SNVS557C – MAY 2008 – REVISED APRIL 2013 www.ti.com OPERATION DESCRIPTION GENERAL The LM20323 switching regulator features all of the functions necessary to implement an efficient buck regulator using a minimum number of external components. This easy to use regulator features two integrated switches and is capable of supplying up to 3A of continuous output current.
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LM20323 www.ti.com SNVS557C – MAY 2008 – REVISED APRIL 2013 PRE-BIAS STARTUP CAPABILITY The LM20323 is in a pre-biased state when it starts up with an output voltage greater than zero. This often occurs in many multi-rail applications such as when powering an FPGA, ASIC, or DSP. In these applications the output can be pre-biased through parasitic conduction paths from one supply rail to another.
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LM20323 SNVS557C – MAY 2008 – REVISED APRIL 2013 www.ti.com The first equation to calculate for any buck converter is duty-cycle. Ignoring conduction losses associated with the FETs and parasitic resistances it can be approximated by: D= VOUT VIN (1) INDUCTOR SELECTION (L) The inductor value is determined based on the operating frequency, load current, ripple current and duty cycle. The inductor selected should have a saturation current rating greater than the peak current limit of the device.
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LM20323 www.ti.
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LM20323 SNVS557C – MAY 2008 – REVISED APRIL 2013 www.ti.com Table 1. Suggested Values for RFB1 and RFB2 RFB1(kΩ) RFB2(kΩ) VOUT short open 0.8 4.99 10 1.2 8.87 10.2 1.5 12.7 10.2 1.8 21.5 10.2 2.5 31.6 10.2 3.3 52.3 10 5.0 If different output voltages are required, RFB2 should be selected to be between 4.99 kΩ to 49.9 kΩ and RFB1 can be calculated using the equation below. RFB1 = VOUT 0.
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LM20323 SNVS557C – MAY 2008 – REVISED APRIL 2013 Output Filter Pole, fP(FIL) AM 0 dB Output Filter Zero, fZ(FIL) Complex Double Pole, fP(MOD) Modulator and Output Filter Transfer Function www.ti.com Pole, fP2(EA) 0 dB Error Amp Zero, fZ(EA) AEA + AM Error Amp Pole, fP(EA) 0 dB Complex Double Pole, fP(MOD) fC Error Amplifier Transfer Function Optional Error Amp Compensated Open Loop Transfer Function GAIN (dB) Error Amp Pole, fP1(EA) AEA fSW/2 FREQUENCY (Hz) Figure 25.
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LM20323 SNVS557C – MAY 2008 – REVISED APRIL 2013 www.ti.com BOOT CAPACITOR (CBOOT) The LM20323 integrates an N-channel buck switch and associated floating high voltage level shift / gate driver. This gate driver circuit works in conjunction with an internal diode and an external bootstrap capacitor. A 0.1 µF ceramic capacitor, connected with short traces between the BOOT pin and SW pin, is recommended.
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LM20323 www.ti.com SNVS557C – MAY 2008 – REVISED APRIL 2013 The value for resistor RB can be selected by the user to control the current through the divider. Typically this resistor will be selected to be between 1 kΩ and 49.9 kΩ. Once the value for RB is chosen the resistor RA can be solved using the equation below to set the desired turn-on voltage.
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LM20323 SNVS557C – MAY 2008 – REVISED APRIL 2013 www.ti.com SIMULTANEOUS START UP VOLTAGE VOUT1 VOUT2 §VOUT2 · -1¸¸ x R2 R1 = ¨¨ © 0.8V ¹ VEN VOUT2 < 0.8 x VOUT1 TIME RATIOMETRIC START UP VOUT1 VOLTAGE VOUT2 R1 = ( VOUT1 -1) x R2 VEN TIME Figure 29. Common Start Up Sequences A simultaneous start up is preferred when powering most FPGAs, DSPs, or other microprocessors. In these systems the higher voltage, VOUT1, usually powers the I/O, and the lower voltage, VOUT2, powers the core.
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LM20323 www.ti.com SNVS557C – MAY 2008 – REVISED APRIL 2013 The external Schottky conducts currents for a very small portion of the switching cycle, therefore the average current is low. An external Schottky rated for 1A will improve efficiency by several percent in some applications. A Schottky rated at a higher current will not significantly improve efficiency and may be worse due to the increased reverse capacitance.
PAGE 20
LM20323 SNVS557C – MAY 2008 – REVISED APRIL 2013 www.ti.com Figure 31. Safe Thermal Operating Areas (IOUT = 2.5A) The dashed lines in the figures above show an approximation of the minimum and maximum duty cycle limitations; while, the solid lines define areas of operation for a given ambient temperature.
PAGE 21
LM20323 www.ti.com SNVS557C – MAY 2008 – REVISED APRIL 2013 2. Minimize the copper area of the switch node. Since the LM20323 has the SW pins on opposite sides of the package it is recommended that the SW pins should be connected with a trace that runs around the package. The inductor should be placed at an equal distance from the SW pins using 100 mil wide traces to minimize capacitive and conductive losses. 3. Have a single point ground for all device grounds located under the EP.
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LM20323 SNVS557C – MAY 2008 – REVISED APRIL 2013 www.ti.com VIN C1 C3 C2 GND C2, C3 should be placed at VIN pins 5,6 and 15,16 respectively. U1 VOUT C4 18 VCC R1 3 ENABLE 19 PGOOD BOOT EN 1 SS 4 COMP 2 FB 12 20 C8 C6 AGND NC LM20323 PGOOD 5 VIN 6 VIN 15 VIN 16 VIN 17 C5 7 SW 8 SW 13 SW 14 SW L1 9 GND 10 GND 11 GND VOUT D1 (OPTIONAL for improved Efficiency) C9 GND EP R3 C7 R2 R4 Figure 34. Typical Application Schematic Table 4. Bill of Materials (VIN = 12V, VOUT = 3.
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LM20323 www.ti.com SNVS557C – MAY 2008 – REVISED APRIL 2013 REVISION HISTORY Changes from Revision B (April 2013) to Revision C • Page Changed layout of National Data Sheet to TI format ..........................................................................................................
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PACKAGE OPTION ADDENDUM www.ti.
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PACKAGE MATERIALS INFORMATION www.ti.com 29-May-2013 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) LM20323MHE/NOPB HTSSOP PWP 20 250 178.0 16.4 LM20323MHX/NOPB HTSSOP PWP 20 2500 330.0 16.4 Pack Materials-Page 1 B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant 6.95 7.1 1.6 8.0 16.0 Q1 6.95 7.1 1.6 8.0 16.
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PACKAGE MATERIALS INFORMATION www.ti.com 29-May-2013 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) LM20323MHE/NOPB HTSSOP PWP LM20323MHX/NOPB HTSSOP PWP 20 250 210.0 185.0 35.0 20 2500 367.0 367.0 35.
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MECHANICAL DATA PWP0020A MXA20A (Rev C) www.ti.
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