Datasheet

PVIN
SW
AGND
FB
PGOOD
EN
SS/TRK
AVIN
COMP
LM20146
L
R
F
VCC
PGND
C
IN
R
C1
C
C1
V
IN
C
SS
C
VCC
C
OUT
V
OUT
R
FB2
R
FB1
C
F
RT
R
T
(optional)
C
C2
PVIN
SW
PGND
L
V
OUT
LM20146
C
IN
C
OUT
LOOP1
LOOP2
LM20146
SNVS563C –FEBRUARY 2008–REVISED APRIL 2013 www.ti.com
2. Minimize the copper area of the switch node. Since the LM20146 has the SW pins on opposite sides of the
package it is recommended to via these pins down to the bottom or internal layer with 2 to 4 vias on each SW
pin. The SW pins should be directly connected with a trace that runs across the bottom of the package. To
minimize IR losses this trace should be no smaller that 50 mils wide, but no larger than 100 mils wide to keep the
copper area to a minimum. In general the SW pins should not be connected on the top layer since it could block
the ground return path for the power ground. The inductor should be placed as close as possible to one of the
SW pins to further minimize the copper area of the switch node.
3. Have a single point ground for all device analog grounds located under the DAP. The ground connections for
the compensation, feedback, and Soft-Start components should be connected together then routed to the AGND
pin of the device. The AGND pin should connect to PGND under the DAP. This prevents any switched or load
currents from flowing in the analog ground plane. If not properly handled poor grounding can result in degraded
load regulation or erratic switching behavior.
4. Minimize trace length to the FB pin. Since the feedback node can be high impedance the trace from the output
resistor divider to FB pin should be as short as possible. This is most important when high value resistors are
used to set the output voltage. The feedback trace should be routed away from the SW pin and inductor to avoid
contaminating the feedback signal with switch noise.
5. Make input and output bus connections as wide as possible. This reduces any voltage drops on the input or
output of the converter and can improve efficiency. If voltage accuracy at the load is important make sure
feedback voltage sense is made at the load. Doing so will correct for voltage drops at the load and provide the
best output accuracy.
6. Provide adequate device heatsinking. Use as many vias as is possible to connect the DAP to the power plane
heatsink. For best results use a 4x4 via array with a minimum via diameter of 12 mils. See the Thermal
Considerations section to insure enough copper heatsinking area is used to keep the junction temperature below
125°C.
Figure 37. Schematic of LM20146 Highlighting Layout Sensitive Nodes
Typical Application Circuits
This section provides several application solutions with a bill of materials. All bill of materials reference the below
figure. The compensation for these solutions were optimized to work over a wide range of input and output
voltages; if a faster transient response is needed reduce the value of C
C1
and calculate the new value for R
C1
as
outlined in the design guide.
Figure 38.
22 Submit Documentation Feedback Copyright © 2008–2013, Texas Instruments Incorporated
Product Folder Links: LM20146