Datasheet

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PVIN

AGND

PGOOD

SS/TRK

AVIN

COMP

LM20136

VCC

PGND

VCC

OUT

FB2

FB1

(optional)

SYNC

LM20136

www.ti.com

SNVS564B –JANUARY 2009–REVISED APRIL 2013

LM20136 6A, Synchronous Buck Regulator with Input Synchronization

Check for Samples: LM20136

FEATURES

DESCRIPTION

The LM20136 is a full featured synchronous buck

• Input Voltage Range 2.95V to 5.5V

regulator capable of delivering up to 6A of continuous

• Accurate Current Limit Minimizes Inductor

output current. The current mode control loop can be

Size

compensated to be stable with virtually any type of

• 97% Peak Efficiency

output capacitor. For most cases, compensating the

device only requires two external components,

• Frequency Synchronization Pin

providing maximum flexibility and ease of use. The

• 16mΩ and 20mΩ Integrated FET Switches

device is optimized to work over the input voltage

• Starts up Into Pre-biased Loads

range of 2.95V to 5.5V making it suitable for a wide

variety of low voltage systems.

• Output Voltage Tracking

• Peak Current Mode Control

The device features internal over voltage protection

(OVP) and over current protection (OCP) circuits for

• Adjustable Output Voltage Down to 0.8V

increased system reliability. A precision enable pin

• Adjustable Soft-Start with External Capacitor

and integrated UVLO allows the turn on of the device

• Precision Enable Pin with Hysteresis

to be tightly controlled and sequenced. Start-up

inrush currents are limited by both an internally fixed

• Integrated OVP, UVLO, Power Good and

and externally adjustable Soft-Start circuit. Fault

Thermal Shutdown

detection and supply sequencing are possible with

• 16-Pin HTSSOP exposed Pad Package

the integrated power good circuit.

The switching frequency of the LM20136 can be

APPLICATIONS

synchronized to an external clock by use of the

• Simple to Design, High Efficiency Point of

SYNC pin. The SYNC pin is capable of synchronizing

Load Regulation from a 5V or 3.3V Bus

to input signals ranging from 500 kHz to 1.5 MHz

• High Performance DSPs, FPGAs, ASICs and

The LM20136 is designed to work well in multi-rail

Microprocessors

power supply architectures. The output voltage of the

• Broadband, Networking and Optical

device can be configured to track a higher voltage rail

using the SS/TRK pin. If the output of the LM20136 is

Communications Infrastructure

pre-biased at startup it will not pull the ouput low.

The LM20136 is offered in a 16-pin HTSSOP

package with an exposed pad that can be soldered to

the PCB, eliminating the need for bulky heatsinks.

Typical Application Circuit

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

2All trademarks are the property of their respective owners.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

Summary of content (31 pages)

PAGE 1
LM20136 www.ti.com SNVS564B – JANUARY 2009 – REVISED APRIL 2013 LM20136 6A, Synchronous Buck Regulator with Input Synchronization Check for Samples: LM20136 FEATURES DESCRIPTION • • The LM20136 is a full featured synchronous buck regulator capable of delivering up to 6A of continuous output current. The current mode control loop can be compensated to be stable with virtually any type of output capacitor.
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LM20136 SNVS564B – JANUARY 2009 – REVISED APRIL 2013 www.ti.com Connection Diagram SS/TRK 1 16 SYNC FB 2 15 AGND PGOOD 3 14 AVIN COMP 4 13 VCC NC 5 12 EN PVIN 6 11 PGND PVIN 7 10 PGND SW 8 9 EP SW Figure 1. Top View 16-Pin HTSSOP See PWP Package PIN DESCRIPTIONS Pin # Name Description 1 SS/TRK Soft-Start or Tracking control input. An internal 5 µA current source charges an external capacitor to set the Soft-Start ramp rate.
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LM20136 www.ti.com SNVS564B – JANUARY 2009 – REVISED APRIL 2013 Absolute Maximum Ratings (1) (2) Voltages from the indicated pins to GND AVIN, PVIN, EN, PGOOD, SS/TRK, COMP, FB, SW, SYNC -0.3V to +6V Storage Temperature -65°C to 150°C Junction Temperature 150°C (3) 2.6W Lead Temperature (Soldering, 10 sec) 260°C Power Dissipation Minimum ESD Rating (4) (1) (2) (3) (4) ±2kV Absolute Maximum Ratings indicate limits beyond which damage to the device may occur.
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LM20136 SNVS564B – JANUARY 2009 – REVISED APRIL 2013 www.ti.com Electrical Characteristics (continued) Unless otherwise stated, the following conditions apply: AVIN = PVIN = VIN = 5V. Limits in standard type are for TJ = 25°C only, limits in bold face type apply over the junction temperature (TJ) range of -40°C to +125°C. Minimum and Maximum limits are specified through test, design, or statistical correlation.
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LM20136 www.ti.com SNVS564B – JANUARY 2009 – REVISED APRIL 2013 Typical Performance Characteristics Unless otherwise specified: CIN = COUT = 100µF, L = 1.0µH (TDK SPM6530T-1R0M120), VIN = 5V, VOUT = 1.2V, RLOAD = 1.2Ω, fSW = 1 MHz, TA = 25°C for efficiency curves, loop gain plots and waveforms, and TJ = 25°C for all others. Efficiency vs. Load Current (VIN = 5V, fSW = 1 MHz) VOUT = 3.3V Efficiency vs. Load Current (VIN = 3.3V, fSW = 1 MHz) VOUT = 2.5V VOUT = 1.5V VOUT = 2.5V VOUT = 1.5V VOUT = 1.
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LM20136 SNVS564B – JANUARY 2009 – REVISED APRIL 2013 www.ti.com Typical Performance Characteristics (continued) Unless otherwise specified: CIN = COUT = 100µF, L = 1.0µH (TDK SPM6530T-1R0M120), VIN = 5V, VOUT = 1.2V, RLOAD = 1.2Ω, fSW = 1 MHz, TA = 25°C for efficiency curves, loop gain plots and waveforms, and TJ = 25°C for all others. 6 Error Amplifier Gain vs. Frequency Line Regulation Figure 8. Figure 9. Load Regulation Feedback Pin Voltage vs. Temperature (TJ) Figure 10. Figure 11.
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LM20136 www.ti.com SNVS564B – JANUARY 2009 – REVISED APRIL 2013 Typical Performance Characteristics (continued) Unless otherwise specified: CIN = COUT = 100µF, L = 1.0µH (TDK SPM6530T-1R0M120), VIN = 5V, VOUT = 1.2V, RLOAD = 1.2Ω, fSW = 1 MHz, TA = 25°C for efficiency curves, loop gain plots and waveforms, and TJ = 25°C for all others. Quiescent Current vs. Temperature (Not Switching) Shutdown Current vs. VIN Figure 14. Figure 15. Enable Threshold vs. Temperature (TJ) UVLO Threshold vs.
PAGE 8
LM20136 SNVS564B – JANUARY 2009 – REVISED APRIL 2013 www.ti.com Typical Performance Characteristics (continued) Unless otherwise specified: CIN = COUT = 100µF, L = 1.0µH (TDK SPM6530T-1R0M120), VIN = 5V, VOUT = 1.2V, RLOAD = 1.2Ω, fSW = 1 MHz, TA = 25°C for efficiency curves, loop gain plots and waveforms, and TJ = 25°C for all others. Peak Current Limit vs. VIN Load Transient Response VOUT (100 mV/Div) IOUT (2A/Div) IOUT (600 mA to 6A) TIME (100 és/DIV) Figure 21. Figure 20.
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LM20136 www.ti.com SNVS564B – JANUARY 2009 – REVISED APRIL 2013 Typical Performance Characteristics (continued) Unless otherwise specified: CIN = COUT = 100µF, L = 1.0µH (TDK SPM6530T-1R0M120), VIN = 5V, VOUT = 1.2V, RLOAD = 1.2Ω, fSW = 1 MHz, TA = 25°C for efficiency curves, loop gain plots and waveforms, and TJ = 25°C for all others. Short Circuit Input Current vs. VIN PGOOD vs. IPGOOD Figure 26. Figure 27.
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LM20136 SNVS564B – JANUARY 2009 – REVISED APRIL 2013 www.ti.com Block Diagram +2.7V REGULATOR AVIN 2.7V VCC UVLO + - SLOPE COMP PVIN COMP 2.7V CURRENT SENSE + 5 PA DISCHARGE (50 Ps) SS/TRK ERROR AMP gm = 510 Pmho + + FB 8.5A VREF + - 800 mV DISCHARGE CURRENT LIMIT + - PVIN + - 864 mV PWM COMPARATOR OVERVOLTAGE + - PG-L 752 mV UNDERVOLTAGE + - DIODE EMULATION CONTROL LOGIC + - SW PVIN THERMAL PROTECTION EN 1.
PAGE 11
LM20136 www.ti.com SNVS564B – JANUARY 2009 – REVISED APRIL 2013 OPERATION DESCRIPTION General The LM20136 switching regulator features all of the functions necessary to implement an efficient low voltage buck regulator using a minimum number of external components. This easy to use regulator features two integrated switches and is capable of supplying up to 6A of continuous output current.
PAGE 12
LM20136 SNVS564B – JANUARY 2009 – REVISED APRIL 2013 www.ti.com Soft-Start and Voltage Tracking The SS/TRK pin is a dual function pin that can be used to set the start up time or track an external voltage source. The start up or Soft-Start time can be adjusted by connecting a capacitor from the SS/TRK pin to ground. The Soft-Start feature allows the regulator output to gradually reach the steady state operating point, thus reducing stresses on the input supply and controlling start up current.
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LM20136 www.ti.com SNVS564B – JANUARY 2009 – REVISED APRIL 2013 CURRENT LIMIT IL Soft Start Time VSS 2.7V 0.8V VOVP VFB FOLDBACK ` VOVPHYS 0.8V VFB VUVP `VPGHYS 0.0V VENABLE TPGOOD VPGOOD FSW FOLDBACK VSWITCH OVPLOW SIDE ON UVP DISABLE PRE-BIASED STARTUP CONDITION CURRENT LIMIT Figure 28. Powergood Behavior UVLO The LM20136 has a built-in under-voltage lockout protection circuit that keeps the device from switching until the input voltage reaches 2.7V (typical).
PAGE 14
LM20136 SNVS564B – JANUARY 2009 – REVISED APRIL 2013 www.ti.com Light Load Operation The LM20136 offers increased efficiency when operating at light loads. Whenever the load current is reduced to a point where the peak to peak inductor ripple current is greater than two times the load current, the part will enter the diode emulation mode preventing significant negative inductor current.
PAGE 15
LM20136 SNVS564B – JANUARY 2009 – REVISED APRIL 2013 Switchnode Voltage www.ti.com Continuous Conduction Mode (CCM) VIN Time (s) Inductor Current Continuous Conduction Mode (CCM) IAVERAGE Inductor Current Time (s) DCM - CCM Boundary IAVERAGE Switchnode Voltage Time (s) Discontinuous Conduction Mode (DCM) VIN Inductor Current Time (s) Discontinuous Conduction Mode (DCM) IPeak Time (s) Figure 29.
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LM20136 SNVS564B – JANUARY 2009 – REVISED APRIL 2013 www.ti.com L LM20136 PVIN SW VIN VOUT RFB1 EN RF AVIN CIN FB CF COUT VIN RFB2 RPG SYNC COMP RC1 CC1 x PGOOD VCC SS/TRK PGND GND VPG CVCC CSS Figure 30. Typical Application Circuit The first equation to calculate for any buck converter is duty-cycle.
PAGE 17
LM20136 www.ti.com SNVS564B – JANUARY 2009 – REVISED APRIL 2013 Output Capacitor Selection (COUT) The output capacitor, COUT, filters the inductor ripple current and provides a source of charge for transient load conditions. A wide range of output capacitors may be used with the LM20136 that provide excellent performance. The best performance is typically obtained using ceramic, SP, or OSCON type chemistries.
PAGE 18
LM20136 SNVS564B – JANUARY 2009 – REVISED APRIL 2013 www.ti.com As indicated by the RMS ripple current equation, highest requirement for RMS current rating occurs at 50% duty cycle. For this case, the RMS ripple current rating of the input capacitor should be greater than half the output current. For best performance, low ESR ceramic capacitors should be placed in parallel with higher capacitance capacitors to provide the best input filtering for the device.
PAGE 19
LM20136 SNVS564B – JANUARY 2009 – REVISED APRIL 2013 Output Filter Pole, fP(FIL) AM 0 dB Output Filter Zero, fZ(FIL) Complex Double Pole, fP(MOD) Modulator and Output Filter Transfer Function www.ti.com Pole, fP2(EA) 0 dB Error Amp Zero, fZ(EA) AEA + AM Error Amp Pole, fP(EA) 0 dB Complex Double Pole, fP(MOD) fC Error Amplifier Transfer Function Optional Error Amp Compensated Open Loop Transfer Function GAIN (dB) Error Amp Pole, fP1(EA) AEA fSW/2 FREQUENCY (Hz) Figure 32.
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LM20136 SNVS564B – JANUARY 2009 – REVISED APRIL 2013 www.ti.com If the output filter zero, (fZ(FIL)) approaches the crossover frequency (FC), an additional capacitor (CC2) should be placed at the COMP pin to ground. This capacitor adds a pole to cancel the output filter zero assuring the crossover frequency will occur before the double pole at fSW/2 degrades the phase margin. The output filter zero is set by the output capacitor value and ESR as shown in the equation below.
PAGE 21
LM20136 www.ti.com SNVS564B – JANUARY 2009 – REVISED APRIL 2013 Using Precision Enable and Power Good The precision enable(EN) and power good(PGOOD) pins of the LM20136 can be used to address many sequencing requirements. The turn-on of the LM20136 can be controlled with the precision enable pin by using two external resistors as shown in Figure 34 External Power Supply VOUT1 LM20136 RA VOUT2 EN RB Figure 34.
PAGE 22
LM20136 SNVS564B – JANUARY 2009 – REVISED APRIL 2013 www.ti.com SIMULTANEOUS START UP VOLTAGE VOUT1 VOUT2 §VOUT2 · -1¸¸ x R2 R1 = ¨¨ © 0.8V ¹ VEN VOUT2 < 0.8 x VOUT1 TIME RATIOMETRIC START UP VOUT1 VOLTAGE VOUT2 R1 = ( VOUT1 -1) x R2 VEN TIME Figure 36. Common Start Up Sequences A simultaneous start up is preferred when powering most FPGAs, DSPs, or other microprocessors. In these systems the higher voltage, VOUT1, usually powers the I/O, and the lower voltage, VOUT2, powers the core.
PAGE 23
LM20136 www.ti.com SNVS564B – JANUARY 2009 – REVISED APRIL 2013 Thermal Considerations The thermal characteristics of the LM20136 are specified using the parameter θJA, which relates the junction temperature to the ambient temperature. Although the value of θJA is dependant on many variables, it still can be used to approximate the operating junction temperature of the device.
PAGE 24
LM20136 SNVS564B – JANUARY 2009 – REVISED APRIL 2013 www.ti.com 2. Minimize the copper area of the switch node. Since the LM20136 has the SW pins on opposite sides of the package it is recommended to via these pins down to the bottom or internal layer with 2 to 4 vias on each SW pin. The SW pins should be directly connected with a trace that runs across the bottom of the package.
PAGE 25
LM20136 www.ti.com SNVS564B – JANUARY 2009 – REVISED APRIL 2013 L LM20136 CIN RFB1 EN RF VOUT SW PVIN VIN FB COUT AVIN RFB2 PGOOD SYNC CF COMP RC1 CC1 VCC SS/TRK PGND AGND CVCC CSS (optional) Figure 39. Bill of Materials (VIN = 5V, VOUT = 3.3V, IOUTMAX = 6A, FSYNC = 500kHz) Designator Description Part Number Manufacturer Qty U1 Synchronous Buck Regulator LM20136 Texas Instruments 1 CIN 100µF, 1210, X5R, 6.3V C3225X5R0J107M TDK 1 COUT 100µF, 1210, X5R, 6.
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LM20136 SNVS564B – JANUARY 2009 – REVISED APRIL 2013 www.ti.com REVISION HISTORY Changes from Revision A (April 2013) to Revision B • 26 Page Changed layout of National Data Sheet to TI format ..........................................................................................................
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PACKAGE OPTION ADDENDUM www.ti.
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PACKAGE MATERIALS INFORMATION www.ti.com 29-May-2013 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) LM20136MHE/NOPB HTSSOP PWP 16 250 178.0 12.4 LM20136MHX/NOPB HTSSOP PWP 16 2500 330.0 12.4 Pack Materials-Page 1 B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant 6.95 8.3 1.6 8.0 12.0 Q1 6.95 8.3 1.6 8.0 12.
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PACKAGE MATERIALS INFORMATION www.ti.com 29-May-2013 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) LM20136MHE/NOPB HTSSOP PWP LM20136MHX/NOPB HTSSOP PWP 16 250 210.0 185.0 35.0 16 2500 367.0 367.0 35.
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MECHANICAL DATA PWP0016A MXA16A (Rev A) www.ti.
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