Datasheet

LM1971

SNAS104B –FEBRUARY 1995–REVISED APRIL 2013

www.ti.com

Pin Descriptions

REF

IN (1): The V

REF

IN pin provides the reference for the analog input signal. This pin should be biased at half of

the supply voltage, V

, as shown in Figure 1 and Figure 19.

OUT (2): The attenuated analog output signal comes from this pin.

GND (3): The GND pin references the digital input signals and is the lower voltage reference for the IC.

Typically this pin would be labeled “V

” but the ground reference for the digital logic input control is tied to

this same point. With a higher pin-count there would generally be separate pins for these functions; V

and Logic Ground. It is intended that the LM1971 always be operated using a single voltage supply

configuration, for which pin 3 (GND) should always be at system ground. If a bipolar or split-supply

configuration are desired, level shifting circuitry is needed for the digital logic control pins as they would be

referenced through pin 3 which would be at the negative supply. It is highly recommended, however, that

the LM1971 be used in a unipolar or single-supply configuration.

LOAD (4): The LOAD input accepts a TTL or CMOS level signal. This is the enable pin of the device, allowing

data to be clocked in while this input is low (0V). The GND pin is the reference for this signal.

DATA (5): The DATA input accepts a TTL or CMOS level signal. This pin is used to accept serial data from a

microcontroller that will be latched and decoded to change the channel's attenuation level. The GND pin is

the reference for this signal.

CLOCK (6): The CLOCK input accepts a TTL or CMOS level signal. The clock input is used to load data into the

internal shift register on the rising edge of the input clock waveform. The GND pin is the reference for this

signal.

(7): The positive voltage supply should be placed to this pin.

IN (8): The analog input signal should be placed to this pin.

Product Folder Links: LM1971