Datasheet

LM1881
SNLS384F –FEBRUARY 1995–REVISED MARCH 2013 www.ti.com
Absolute Maximum Ratings
(1)(2)
Supply Voltage 13.2V
Input Voltage 3 V
P-P
(V
CC
= 5V)
6 V
P-P
(V
CC
≥ 8V)
Output Sink Currents; Pins, 1, 3, 5 5 mA
Output Sink Current; Pin 7 2 mA
Package Dissipation
(3)
1100 mW
Storage Temperature Range −65°C to +150°C
ESD Susceptibility
(4)
2 kV
ESD Susceptibility
(5)
200 V
Soldering Information PDIP Package (10 sec.) 260°C
SOIC Package Vapor Phase (60 sec.) 215°C
Infrared (15 sec.) 220°C
(1) Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. For ensured specifications and test
conditions, see the Electrical Characteristics. The ensured specifications apply only for the test conditions listed.
(2) If Military/Aerospace specified devices are required, please contact the TI Sales Office/ Distributors for availability and specifications.
(3) For operation in ambient temperatures above 25°C, the device must be derated based on a 150°C maximum junction temperature and a
package thermal resistance of 110°C/W, junction to ambient.
(4) ESD susceptibility test uses the “human body model, 100 pF discharged through a 1.5 kΩ resistor”.
(5) Machine Model, 220 pF – 240 pF discharged through all pins.
Electrical Characteristics LM1881
V
CC
= 5V; R
SET
= 680 kΩ; T
A
= 0°C to +70°C by correlation with 100% electrical testing at T
A
=25°C
Parameter Conditions Min Typ
(1)
Max Units
Supply Current Outputs at V
CC
= 5V 5.2 10
mA
Logic 1 V
CC
= 12V 5.5 12
DC Input Voltage Pin 2 1.3 1.5 1.8 V
Input Threshold Voltage
(2)
55 70 85 mV
Input Discharge Current Pin 2; V
IN
= 2V 6 11 16 µA
Input Clamp Charge Current Pin 2; V
IN
= 1V 0.2 0.8 mA
R
SET
Pin Reference Voltage Pin 6;
(3)
1.10 1.22 1.35 V
Composite Sync. & Vertical I
OUT
= 40 µA; V
CC
= 5V 4.0 4.5
V
Outputs Logic 1 V
CC
= 12V 11.0
I
OUT
= 1.6 mA V
CC
= 5V 2.4 3.6
V
Logic 1 V
CC
= 12V 10.0
Burst Gate & Odd/Even Outputs I
OUT
= 40 µA; V
CC
= 5V 4.0 4.5
V
Logic 1 V
CC
= 12V 11.0
Composite Sync. Output I
OUT
= −1.6 mA; Logic 0; Pin 1 0.2 0.8 V
Vertical Sync. Output I
OUT
= −1.6 mA; Logic 0; Pin 3 0.2 0.8 V
Burst Gate Output I
OUT
= −1.6 mA; Logic 0; Pin 5 0.2 0.8 V
Odd/Even Output I
OUT
= −1.6 mA; Logic 0; Pin 7 0.2 0.8 V
Vertical Sync Width 190 230 300 µs
Burst Gate Width 2.7 kΩ from Pin 5 to V
CC
2.5 4 4.7 µs
Vertical Default Time
(4)
32 65 90 µs
(1) Typicals are at T
J
= 25°C and represent the most likely parametric norm.
(2) Relative difference between the input clamp voltage and the minimum input voltage which produces a horizontal output pulse.
(3) Careful attention should be made to prevent parasitic capacitance coupling from any output pin (Pins 1, 3, 5 and 7) to the R
SET
pin (Pin
6).
(4) Delay time between the start of vertical sync (at input) and the vertical output pulse.
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