Datasheet

LM13700
SNOSBW2E –NOVEMBER 1999–REVISED MARCH 2013 www.ti.com
Figure 39. Single Amplifier VCO
Additional Applications
Figure 40 presents an interesting one-shot which draws no power supply current until it is triggered. A positive-
going trigger pulse of at least 2V amplitude turns on the amplifier through R
B
and pulls the non-inverting input
high. The amplifier regenerates and latches its output high until capacitor C charges to the voltage level on the
non-inverting input. The output then switches low, turning off the amplifier and discharging the capacitor. The
capacitor discharge rate is speeded up by shorting the diode bias pin to the inverting input so that an additional
discharge current flows through D
I
when the amplifier output switches low. A special feature of this timer is that
the other amplifier, when biased from V
O
, can perform another function and draw zero stand-by power as well.
Figure 40. Zero Stand-By Power Timer
The operation of the multiplexer of Figure 41 is very straightforward. When A1 is turned on it holds V
O
equal to
V
IN1
and when A2 is supplied with bias current then it controls V
O
. C
C
and R
C
serve to stabilize the unity-gain
configuration of amplifiers A1 and A2. The maximum clock rate is limited to about 200 kHz by the LM13700 slew
rate into 150 pF when the (V
IN1
–V
IN2
) differential is at its maximum allowable value of 5V.
The Phase-Locked Loop of Figure 42 uses the four-quadrant multiplier of Figure 27 and the VCO of Figure 39 to
produce a PLL with a ±5% hold-in range and an input sensitivity of about 300 mV.
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