Datasheet

LM12L458
SNAS085B –JULY 1999–REVISED MARCH 2013 www.ti.com
Digital Timing Characteristics (continued)
The following specifications apply for V
A
+ = V
D
+ = +3.3V, t
r
= t
f
= 3 ns, and C
L
= 100 pF on data I/O, INT and DMARQ lines
unless otherwise specified. Boldface limits apply for T
A
= T
J
= T
MIN
to T
MAX
; all other limits T
A
= T
J
= 25°C.
(1)(2)(3)
Symbol (See
Figure 28 Figure 29 Parameter Conditions Typical
(4)
Limits
(5)
Units
Figure 30)
14 Data Valid to WR High Set-Up Time 40 ns (min)
15 Data Valid to WR High Hold Time 30 ns (min)
ns (min)
10
16 RD Low to Data Bus Out of TRI-STATE 30
70
ns (max)
ns (min)
10
17 RD High to TRI-STATE R
L
= 1 kΩ 30
110
ns (max)
ns (min)
10
18 RD Low to Data Valid (Access Time) 30
95
ns (max)
20 Address Valid or CS Low to RD Low 20 ns (min)
21 Address Valid or CS Low to WR Low 20 ns (min)
19 Address Invalid from RD or WR High 10 ns (min)
ns (min)
10
22 INT High from RD Low 30
60
ns (max)
ns (min)
10
23 DMARQ Low from RD Low 30
60
ns (max)
Figure 3.
Test Circuits and Waveforms
Figure 4. TRI-STATE Test Circuits and Waveforms
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