Datasheet

LM12L458
www.ti.com SNAS085B –JULY 1999–REVISED MARCH 2013
Converter Characteristics (continued)
The following specifications apply for V
A
+ = V
D
+ = +3.3V, V
REF+
= +2.5V, V
REF−
= 0V, 12-bit + sign conversion mode, f
CLK
=
6.0 MHz, R
S
= 25Ω, source impedance for V
REF+
and V
REF−
≤ 25Ω, fully-differential input with fixed 1.25V common-mode
voltage, and minimum acquisition time unless otherwise specified. Boldface limits apply for T
A
= T
J
= T
MIN
to T
MAX
; all other
limits T
A
= T
J
= 25°C
(1)(2)(3)(4)
Symbol Parameter Conditions Typical
(5)
Limits
(6)
Units
Zero Error V
A
+ = V
D
+ = +3.3V ±10% ±0.2 ±1.75 LSB (max)
Power Supply
PSS Full-Scale Error V
REF+
= 2.5V, V
REF−
= GND ±0.4 ±2 LSB (max)
Sensitivity
(11)
Linearity Error ±0.2 LSB
C
REF
V
REF+
/V
REF−
Input Capacitance 85 pF
Selected Multiplexer Channel Input
C
IN
75 pF
Capacitance
(11) Power Supply Sensitivity is measured after Auto-Zero and/or Auto-Calibration cycle has been completed with V
A
+ and V
D
+ at the
specified extremes.
Converter AC Characteristics
The following specifications apply for V
A
+ = V
D
+ = +3.3V, V
REF+
= +2.5V, V
REF−
= 0V, 12-bit + sign conversion mode, f
CLK
=
6.0 MHz, R
S
= 25Ω, source impedance for V
REF+
and V
REF−
≤ 25Ω, fully-differential input with fixed +1.25V common-mode
voltage, and minimum acquisition time unless otherwise specified. Boldface limits apply for T
A
= T
J
= T
MIN
to T
MAX
; all other
limits T
A
= T
J
= 25°C.
(1)(2)(3) (4)
Symbol Parameter Conditions Typical
(5)
Limits
(6)
Units
40 % (min)
Clock Duty Cycle 50
60 % (max)
13-Bit Resolution, Sequencer State
44 (t
CLK
) 44 (t
CLK
) + 50 ns (max)
S5 (Figure 31)
t
C
Conversion Time
9-Bit Resolution, Sequencer State
21 (t
CLK
) 21 (t
CLK
) + 50 ns (max)
S5 (Figure 31)
Sequencer State S7 (Figure 31)
9 (t
CLK
) 9 (t
CLK
) + 50 ns (max)
Built-in minimum for 13-Bits
t
A
Acquisition Time
Built-in minimum for 9-Bits and
2 (t
CLK
) 2 (t
CLK
) + 50 ns (max)
“Watchdog” mode
t
Z
Auto-Zero Time Sequencer State S2 (Figure 31) 76 (t
CLK
) 76 (t
CLK
) + 50 ns (max)
t
CAL
Full Calibration Time Sequencer State S2 (Figure 31) 4944 (t
CLK
) 4944 (t
CLK
) + 50 ns (max)
Throughput Rate
(7)
107 106 kHz (min)
t
WD
Sequencer States S6, S4, and S5
“Watchdog” Mode Comparison Time 11 (t
CLK
) 11 (t
CLK
) + 50 ns (max)
(Figure 31)
t
PU
Power-Up Time 10 ms
t
WU
Wake-Up Time 10 ms
(1) Two on-chip diodes are tied to each analog input through a series resistor, as shown below. Input voltage magnitude up to 5V above
V
A
+ or 5V below GND will not damage the LM12L458. However, errors in the A/D conversion can occur if these diodes are forward
biased by more than 100 mV. As an example, if V
A
+ is 3.0 V
DC
, full-scale input voltage must be =3.1 V
DC
to ensure accurate
conversions. See Figure 3
(2) V
A
+ and V
D
+ must be connected together to the same power supply voltage and bypassed with separate capacitors at each V
+
pin to
assure conversion/comparison accuracy.
(3) Accuracy is ensured when operating at f
CLK
= 6 MHz.
(4) With the test condition for V
REF
= V
REF+
- V
REF-
given as +2.5V, the 12-bit LSB is 305 µV and the 8-bit/“Watchdog” LSB is 4.88 mV.
(5) Typical figures are at T
A
= 25°C and represent most likely parametric norm.
(6) Limits are specified to AOQL (Average Output Quality Level).
(7) The Throughput Rate is for a single instruction repeated continuously. Sequencer states 0 (1 clock cycle), 1 (1 clock cycle), 7 (9 clock
cycles) and 5 (44 clock cycles) are used (see Figure 31). One additional clock cycle is used to read the conversion result stored in the
FIFO, for a total of 56 clock cycles per conversion. The Throughput Rate is f
CLK
(MHz)/N, where N is the number of clock
cycles/conversion.
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