Datasheet

LM12L458
SNAS085B –JULY 1999–REVISED MARCH 2013 www.ti.com
State 5: Perform a conversion or second comparison. This state takes 44 clock cycles when using the 12-bit +
sign mode or 21 clock cycles when using the 8-bit + sign mode. The “watchdog” mode takes 5 clock cycles.
Figure 31. Sequencer Logic Flow Chart (IP = Instruction Pointer)
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