Datasheet

LM12L458
www.ti.com SNAS085B –JULY 1999–REVISED MARCH 2013
Bits 13–15 hold either the instruction responsible for the associated conversion data or the sign bit. Either mode
is selected with Bit 5 in the Configuration register.
Using the FIFO's full depth is achieved as follows. Set the value of the Interrupt Enable registers's Bits 11–15 to
1111 and the Interrupt Enable register's Bit 2 to a “1”. This generates an external interrupt when the 31st
conversion is stored in the FIFO. This gives the host processor a chance to send a “0” to the LM12L458's Start
bit (Configuration register) and halt the ADC before it completes the 32nd conversion. The Sequencer halts after
the current (32) conversion is completed. The conversion data is then transferred to the FIFO and occupies the
32nd location. FIFO overflow is avoided if the Sequencer is halted before the start of the 32nd conversion by
placing a “0” in the Start bit (Configuration register). It is important to remember that the Sequencer continues to
operate even if a FIFO interrupt (INT 2) is internally or externally generated. The only mechanisms that stop
the Sequencer are an instruction with the PAUSE bit set to “1” (halts before instruction execution), placing a “0”
in the Configuration register's START bit, or placing a “1” in the Configuration register's RESET bit.
Sequencer
The Sequencer uses a 3-bit counter (Instruction Pointer, or IP, in Figure 4) to retrieve the programmable
conversion instructions stored in the Instruction RAM. The 3-bit counter is reset to 000 during chip reset or if the
current executed instruction has its Loop bit (Bit 1 in any Instruction RAM “00”) set high (“1”). It increments at the
end of the currently executed instruction and points to the next instruction. It will continue to increment up to 111
unless an instruction's Loop bit is set. If this bit is set, the counter resets to “000” and execution begins again with
the first instruction. If all instructions have their Loop bit reset to “0”, the Sequencer will execute all eight
instructions continuously. Therefore, it is important to realize that if less than eight instructions are programmed,
the Loop bit on the last instruction must be set. Leaving this bit reset to “0” allows the Sequencer to execute
“unprogrammed” instructions, the results of which may be unpredictable.
The Sequencer's Instruction Pointer value is readable at any time and is found in the Status register at Bits 8–10.
The Sequencer can go through eight states during instruction execution:
State 0: The current instruction's first 16 bits are read from the Instruction RAM “00”. This state is one clock
cycle long.
State 1: Checks the state of the Calibration and Start bits. This is the “rest” state whenever the Sequencer is
stopped using the reset, a Pause command, or the Start bit is reset low (“0”). When the Start bit is set to a “1”,
this state is one clock cycle long.
State 2: Perform calibration. If bit 2 or bit 6 of the Configuration register is set to a “1”, state 2 is 76 clock
cycles long. If the Configuration register's bit 3 is set to a “1”, state 2 is 4944 clock cycles long.
State 3: Run the internal 16-bit Timer. The number of clock cycles for this state varies according to the value
stored in the Timer register. The number of clock cycles is found by using the expression below
32T + 2
where
• 0 ≤ T ≤ 2
16
−1 (3)
State 7: Run the acquisition delay and read Limit #1's value if needed. The number of clock cycles for 12-bit +
sign mode varies according to
9 + 2D
where
• D is the user-programmable 4-bit value stored in bits 12–15 of Instruction RAM “00” and is limited to 0 ≤ D ≤
15 (4)
The number of clock cycles for 8-bit + sign or “watchdog” mode varies according to
2 + 2D
where
• D is the user-programmable 4-bit value stored in bits 12–15 of Instruction RAM “00” and is limited to 0 ≤ D ≤
15 (5)
State 6: Perform first comparison. This state is 5 clock cycles long.
State 4: Read Limit #2. This state is 1 clock cycle long.
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