Datasheet

LM12L458
SNAS085B –JULY 1999–REVISED MARCH 2013 www.ti.com
Bits 0–7 show the Limit #1 status. Each bit will be set high (“1”) when the corresponding instruction's input
voltage exceeds the threshold stored in the instruction's Limit #1 register. When, for example, instruction 3 is a
“watchdog” operation (Bit 11 is set high) and the input for instruction 3 meets the magnitude and/or polarity data
stored in instruction 3's Limit #1 register, Bit 3 in the Limit Status register will be set to a “1”.
Bits 8–15 show the Limit #2 status. Each bit will be set high (“1”) when the corresponding instruction's input
voltage exceeds the threshold stored in the instruction's Limit #2 register. When, for example, the input to
instruction 6 meets the value stored in instruction 6's Limit #2 register, Bit 14 in the Limit Status register will be
set to a “1”.
TIMER
The LM12L458 have an on-board 16-bit timer that includes a 5-bit pre-scaler. It uses the clock signal applied to
pin 23 as its input. It can generate time intervals of 0 through 2
21
clock cycles in steps of 2
5
. This time interval
can be used to delay the execution of instructions. It can also be used to slow the conversion rate when
converting slowly changing signals. This can reduce the amount of redundant data stored in the FIFO and
retrieved by the controller.
The user-defined timing value used by the Timer is stored in the 16-bit READ/WRITE Timer register at location
1011 (A4–A1, BW = 0) or 1011x (A4–A0, BW = 1) and is pre-loaded automatically. Bits 0–7 hold the preset
value's low byte and Bits 8–15 hold the high byte. The Timer is activated by the Sequencer only if the current
instruction's Bit 9 is set (“1”). If the equivalent decimal value “N” (0 ≤ N ≤ 2
16
− 1) is written inside the 16-bit Timer
register and the Timer is enabled by setting an instruction's bit 9 to a “1”, the Sequencer will delay the same
instruction's execution by halting at state 3 (S3), as shown in Figure 31, for 32 × N + 2 clock cycles.
DMA
The DMA works in tandem with Interrupt 2. An active DMA Request on pin 32 (DMARQ) requires that the FIFO
interrupt be enabled. The voltage on the DMARQ pin goes high when the number of conversions in the FIFO
equals the 5-bit value stored in the Interrupt Enable register (bits 11–15). The voltage on the INT pin goes low at
the same time as the voltage on the DMARQ pin goes high. The voltage on the DMARQ pin goes low when the
FIFO is emptied. The Interrupt Status register must be read to clear the FIFO interrupt flag in order to enable the
next DMA request.
DMA operation is optimized through the use of the 16-bit data bus connection (a logic “0” applied to the BW pin).
Using this bus width allows DMA controllers that have single address Read/Write capability to easily unload the
FIFO. Using DMA on an 8-bit data bus is more difficult. Two read operations (low byte, high byte) are needed to
retrieve each conversion result from the FIFO. Therefore, the DMA controller must be able to repeatedly access
two constant addresses when transferring data from the LM12L458 to the host system.
FIFO
The result of each conversion stored in an internal read-only FIFO (First-In, First-Out) register. It is located at
1100 (A4–A1, BW = 0) or 1100x (A4–A0, BW = 1). This register has 32 16-bit wide locations. Each location holds
13-bit data. Bits 0–3 hold the four LSB's in the 12 bits + sign mode or “1110” in the 8 bits + sign mode. Bits 4–11
hold the eight MSB's and Bit 12 holds the sign bit. Bits 13–15 can hold either the sign bit, extending the register's
two's complement data format to a full sixteen bits or the instruction address that generated the conversion and
the resulting data. These modes are selected according to the logic state of the Configuration register's Bit 5.
The FIFO status should be read in the Interrupt Status register (Bits 11–15) to determine the number of
conversion results that are held in the FIFO before retrieving them. This will help prevent conversion data
corruption that may take place if the number of reads are greater than the number of conversion results
contained in the FIFO. Trying to read the FIFO when it is empty may corrupt new data being written into the
FIFO. Writing more than 32 conversion data into the FIFO by the ADC results in loss of the first conversion data.
Therefore, to prevent data loss, it is recommended that the LM12L458's interrupt capability be used to inform the
system controller that the FIFO is full.
The lower portion (A0 = 0) of the data word (Bits 0–7) should be read first followed by a read of the upper portion
(A0 = 1) when using the 8-bit bus width (BW = 1). Reading the upper portion first causes the data to shift down,
which results in loss of the lower byte.
Bits 0–12 hold 12-bit + sign conversion data. Bits 0–3 will be 1110 (LSB) when using 8-bit plus sign resolution.
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