Datasheet

LM12L458

www.ti.com

SNAS085B –JULY 1999–REVISED MARCH 2013

Bit 5 enables an external interrupt when an internal Pause interrupt has been generated.

Bit 6 is a “Don't Care”.

Bit 7 enables an external interrupt when the LM12L458 return from power-down to active mode.

Bits 8–10 form the storage location of the user-programmable value against which the Sequencer's address is

compared. When the Sequencer reaches an address that is equal to the value stored in Bits 8–10, an internal

interrupt is generated and appears in Bit 1 of the Interrupt Status register. If Bit 1 of the Interrupt Enable register

is set to “1”, an external interrupt will appear at pin 31 (INT).

The value stored in bits 8–10 ranges from 000 to 111, representing 0 to 7 instructions stored in the Instruction

RAM. After the Instruction RAM has been programmed and the RESET bit is set to “1”, the Sequencer is started

by placing a “1” in the Configuration register's START bit. Setting the INT 1 trigger value to 000 does not

generate an INT 1 the first time the Sequencer retrieves and decodes Instruction 000. The Sequencer

generates INT 1 (by placing a “1” in the Interrupt Status register's Bit 1) the second time and after the

Sequencer encounters Instruction 000. It is important to remember that the Sequencer continues to operate even

if an Instruction interrupt (INT 1) is internally or externally generated. The only mechanisms that stop the

Sequencer are an instruction with the PAUSE bit set to “1” (halts before instruction execution), placing a “0” in

the Configuration register's START bit, or placing a “1” in the Configuration register's RESET bit.

Bits 11–15 hold the number of conversions that must be stored in the Conversion FIFO in order to generate an

internal interrupt. This internal interrupt appears in Bit 2 of the Interrupt Status register. If Bit 2 of the Interrupt

Enable register is set to “1”, an external interrupt will appear at pin 31 (INT).

Other Registers and Functions

INTERRUPT STATUS REGISTER

This read-only register is located at address 1010 (A4–A1, BW = 0) or 1010x (A4–A0, BW = 1). The

corresponding flag in the Interrupt Status register goes high (“1”) any time that an interrupt condition takes place,

whether an interrupt is enabled or disabled in the Interrupt Enable register. Any of the active (“1”) Interrupt Status

Configuration Register).

Bit 0 is set to “1” when a “watchdog” comparison limit interrupt has taken place.

Bit 1 is set to “1” when the Sequencer has reached the address stored in Bits 8–10 of the Interrupt Enable

Bit 2 is set to “1” when the Conversion FIFO's limit, stored in Bits 11–15 of the Interrupt Enable register, has

been reached.

Bit 3 is set to “1” when the single-sampled auto-zero has been completed.

Bit 4 is set to “1” when an auto-zero and full linearity self-calibration has been completed.

Bit 5 is set to “1” when a Pause interrupt has been generated.

Bit 6 is a “Don't Care”.

Bit 7 is set to “1” when the LM12L458 return from power-down to active mode.

Bits 8–10 hold the Sequencer's actual instruction address while it is running.

Bits 11–15 hold the actual number of conversions stored in the Conversion FIFO while the Sequencer is running.

LIMIT STATUS REGISTER

The read-only register is located at address 1101 (A4–A1, BW = 0) or 1101x (A4–A0, BW = 1). This register is

used in tandem with the Limit #1 and Limit #2 registers in the Instruction RAM. Whenever a given instruction's

input voltage exceeds the limit set in its corresponding Limit register (#1 or #2), a bit, corresponding to the

instruction number, is set in the Limit Status register. Any of the active (“1”) Limit Status flags are reset to “0”

whenever this register is read or a device reset is issued (see Bit 1 in the Configuration register). This register

holds the status of limits #1 and #2 for each of the eight instructions.

Product Folder Links: LM12L458