Datasheet

LM12L458
SNAS085B –JULY 1999–REVISED MARCH 2013 www.ti.com
Table 4. LM12L458 Input Multiplexer
Channel Configuration Showing Normal
Mode and Diagnostic Mode
Channel Selection Data Normal Mode Diagnostic Mode
V
IN+
V
IN−
V
IN+
V
IN−
000 IN0 GND
001 IN1 IN1 V
REF+
V
REF−
010 IN2 IN2 IN2 IN2
011 IN3 IN3 IN3 IN3
100 IN4 IN4 IN4 IN4
101 IN5 IN5 IN5 IN5
110 IN6 IN6 IN6 IN6
111 IN7 IN7 IN7 IN7
The Interrupt Status register, 1010 (A4–A1, BW = 0) or 1010x (A4–A0, BW = 1) must be cleared by reading it
after writing to the Interrupt Enable register. This removes any spurious interrupts on the INT pin generated
during an Interrupt Enable register access.
Interrupt 0 is generated whenever the analog input voltage on a selected multiplexer channel crosses a limit
while the LM12L458 are operating in the “watchdog” comparison mode. Two sequential comparisons are made
when the LM12L458 are executing a “watchdog” instruction. Depending on the logic state of Bit 9 in the
Instruction RAM's second and third sections, an interrupt will be generated either when the input signal's
magnitude is greater than or less than the programmable limits. (See the Instruction RAM, Bit 9 description.) The
Limit Status register will indicate which programmed limit, #1 or #2 and which instruction was executing when the
limit was crossed.
Interrupt 1 is generated when the Sequencer reaches the instruction counter value specified in the Interrupt
Enable register's bits 8–10. This flag appears before the instruction's execution.
Interrupt 2 is activated when the Conversion FIFO holds a number of conversions equal to the programmable
value stored in the Interrupt Enable register's Bits 11–15. This value ranges from 0001 to 1111, representing 1 to
31 conversions stored in the FIFO. A user-programmed value of 0000 has no meaning. See Other Registers and
Functions for more FIFO information.
The completion of the short, single-sampled auto-zero calibration generates Interrupt 3.
The completion of a full auto-zero and linearity self-calibration generates Interrupt 4.
Interrupt 5 is generated when the Sequencer encounters an instruction that has its Pause bit (Bit 1 in Instruction
RAM “00”) set to “1”.
Interrupt 7 is issued after a short delay (10 ms typ) while the LM12L458 returns from Standby mode to active
operation using the Configuration register's Bit 4. This short delay allows the internal analog circuitry to settle
sufficiently, ensuring accurate conversion results.
INTERRUPT ENABLE REGISTER
The Interrupt Enable register at address location 1001 (A4–A1, BW = 0) or 1001x (A4–A0, BW = 1) has
READ/WRITE capability. An individual interrupt's ability to produce an external interrupt at pin 31 (INT) is
accomplished by placing a “1” in the appropriate bit location. Any of the internal interrupt-producing operations
will set their corresponding bits to “1” in the Interrupt Status register regardless of the state of the associated bit
in the Interrupt Enable register. See Section 2.3 for more information about each of the eight internal interrupts.
Bit 0 enables an external interrupt when an internal “watchdog” comparison limit interrupt has taken place.
Bit 1 enables an external interrupt when the Sequencer has reached the address stored in Bits 8–10 of the
Interrupt Enable register.
Bit 2 enables an external interrupt when the Conversion FIFO's limit, stored in Bits 11–15 of the Interrupt Enable
register, has been reached.
Bit 3 enables an external interrupt when the single-sampled auto-zero calibration has been completed.
Bit 4 enables an external interrupt when a full auto-zero and linearity self-calibration has been completed.
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