Datasheet
LM12L458
www.ti.com
SNAS085B –JULY 1999–REVISED MARCH 2013
Table 3. LM12L458 Memory Map for 8-Bit Wide Data Bus
(1)
A4 A3 A2 A1 A0 Purpose Type D7 D6 D5 D4 D3 D2 D1 D0
0 0 0
0 to 0 R/W V
IN−
V
IN+
Pause Loop
1 1 1
Instruction RAM
(RAM Pointer = 00)
0 0 0
Watch-
0 to 1 R/W Acquisition Time 8/12 Timer Sync
dog
1 1 1
0 0 0
0 to 0 R/W Comparison Limit #1
1 1 1
Instruction RAM
(RAM Pointer = 01)
0 0 0
0 to 1 R/W Don't Care >/< Sign
1 1 1
0 0 0
0 to 0 R/W Comparison Limit #2
1 1 1
Instruction RAM
(RAM Pointer = 10)
0 0 0
0 to 1 R/W Don't Care >/< Sign
1 1 1
1 0 0 0 0 R/W I/O Sel Auto Zero
ec
Chan Mask Stand- by Full Cal Auto- Zero Reset Start
Configuration
Test
Register
1 0 0 0 1 R/W Don't Care DIAG RAM Pointer
= 0
1 0 0 1 0 R/W INT7 Don't Care INT5 INT4 INT3 INT2 INT1 INT0
Interrupt Enable
Sequencer Address to Generate
Register
1 0 0 1 1 R/W Number of Conversions in Conversion FIFO to Generate INT2
INT1
1 0 1 0 0 R INST7 “0” INST5 INST4 INST3 INST2 INST1 INST0
Interrupt Status
Address of Sequencer Instruction
Register
1 0 1 0 1 R Actual Number of Conversions Results in Conversion FIFO
being Executed
1 0 1 1 0 Timer R/W Timer Preset: Low Byte
Register
1 0 1 1 1 R/W Timer Preset: High Byte
1 1 0 0 0 R Conversion Data: LSBs
Conversion
FIFO
1 1 0 0 1 R Address or Sign Sign Conversion Data: MSBs
1 1 0 1 0 R Limit #1 Status
Limit Status
Register
1 1 0 1 1 R Limit #2 Status
(1) (BW = “1” and Test Bit = “0”)
Bits 12–15 are used to store the user-programmable acquisition time. The Sequencer keeps the internal S/H in
the acquisition mode for a fixed number of clock cycles (nine clock cycles, for 12-bit + sign conversions and two
clock cycles for 8-bit + sign conversions or “watchdog” comparisons) plus a variable number of clock cycles
equal to twice the value stored in Bits 12–15. Thus, the S/H's acquisition time is (9 + 2D) clock cycles for 12-bit +
sign conversions and (2 + 2D) clock cycles for 8-bit + sign conversions or “watchdog” comparisons, where D is
the value stored in Bits 12–15. The minimum acquisition time compensates for the typical internal multiplexer
series resistance of 2 kΩ, and any additional delay created by Bits 12–15 compensates for source resistances
greater than 80Ω. (For this acquisition time discussion, numbers in ( ) are shown for the LM12L458 operating at
6 MHz.) The necessary acquisition time is determined by the source impedance at the multiplexer input. If the
source resistance (R
S
) < 80Ω and the clock frequency is 6 MHz, the value stored in bits 12–15 (D) can be 0000.
If R
S
> 80Ω, the following equations determine the value that should be stored in bits 12–15.
D = 0.45 x R
S
x f
CLK
(1)
for 12-bits + sign
D = 0.36 x R
S
x f
CLK
(2)
for 8-bits + sign and “watchdog”
R
S
is in kΩ and f
CLK
is in MHz. Round the result to the next higher integer value. If D is greater than 15, it is
advisable to lower the source impedance by using an analog buffer between the signal source and the
LM12L458's multiplexer inputs.
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