Datasheet

LM12L458

SNAS085B –JULY 1999–REVISED MARCH 2013

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Table 2. LM12L458 Memory Map for 16-Bit Wide Data Bus

(1)

A4 A3 A2 A1 Purpose Type D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0

0 0 0

Instruction RAM (RAM

0 to R/W Acquisition Time Watch- dog 8/12 Timer Sync V

IN−

IN+

Pause Loop

Pointer = 00)

1 1 1

0 0 0

Instruction RAM (RAM

0 to R/W Don't Care >/< Sign Limit #1

Pointer = 01)

1 1 1

0 0 0

Instruction RAM (RAM

0 to R/W Don't Care >/< Sign Limit #2

Pointer = 10)

1 1 1

Test = Auto Chan Auto-

1 0 0 0 Configuration Register R/W Don't Care DIAG RAM Pointer I/O Sel Stand- by Full CAL Reset Start

0 Zero

Mask Zero

Number of Conversions in Conversion FIFO to Sequencer Address to Don't

1 0 0 1 Interrupt Enable Register R/W INT7 INT6 INT4 INT3 INT2 INT1 INT0

Generate INT2 Generate INT1 Care

Actual Number of Conversion Results in Conversion Address of Sequencer

1 0 1 0 Interrupt Status Register R INST7 “0” INST5 INST4 INST3 INST2 INST1 INST0

FIFO Instruction Being Executed

1 0 1 1 Timer Register R/W Timer Preset High Byte Timer Preset Low Byte

1 1 0 0 Conversion FIFO R Address or Sign Sign Conversion Data: MSBs Conversion Data: LSBs

1 1 0 1 Limit Status Register R Limit #2: Status Limit #1: Status

(1) (BW = “0”, Test Bit = “0” and A0 = Don't Care)

Product Folder Links: LM12L458