Datasheet

LM12L458

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SNAS085B –JULY 1999–REVISED MARCH 2013

Bits 5–7 select which of the seven input channels (“001” to “111” for IN1 to IN7) will be configured as inverting

inputs to the LM12L458's ADC. (See Table 4.) Fully differential operation is created by selecting two multiplexer

channels, one operating in the non-inverting mode and the other operating in the inverting mode. A code of “000”

selects ground as the inverting input for single ended operation.

Bit 8 is the SYNC bit. Setting Bit 8 to “1” causes the Sequencer to suspend operation at the end of the internal

S/H's acquisition cycle and to wait until a rising edge appears at the SYNC pin. When a rising edge appears, the

S/H acquires the input signal magnitude and the ADC performs a conversion on the clock's next rising edge.

When the SYNC pin is used as an input, the Configuration register's “I/O Select” bit (Bit 7) must be set to a “0”.

With SYNC configured as an input, it is possible to synchronize the start of a conversion to an external event.

This is useful in applications such as digital signal processing (DSP) where the exact timing of conversions is

important.

When the LM12L458 is used in the “watchdog” mode with external synchronization, two rising edges on the

SYNC input are required to initiate two comparisons. The first rising edge initiates the comparison of the selected

analog input signal with Limit #1 (found in Instruction RAM “01”) and the second rising edge initiates the

comparison of the same analog input signal with Limit #2 (found in Instruction RAM “10”).

Bit 9 is the TIMER bit. When Bit 9 is set to “1”, the Sequencer will halt until the internal 16-bit Timer counts down

to zero. During this time interval, no “watchdog” comparisons or analog-to-digital conversions will be performed.

Bit 10 selects the ADC conversion resolution. Setting Bit 10 to “1” selects 8-bit + sign and when reset to “0”

selects 12-bit + sign.

Bit 11 is the “watchdog” comparison mode enable bit. When operating in the “watchdog” comparison mode, the

selected analog input signal is compared with the programmable values stored in Limit #1 and Limit #2 (see

Instruction RAM “01” and Instruction RAM “10”). Setting Bit 11 to “1” causes two comparisons of the selected

analog input signal with the two stored limits. When Bit 11 is reset to “0”, an 8-bit + sign or 12-bit + sign

(depending on the state of Bit 10 of Instruction RAM “00”) conversion of the input signal can take place.

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