Datasheet

LM12L458
SNAS085B –JULY 1999–REVISED MARCH 2013 www.ti.com
Microprocessor overhead is reduced through the use of the internal conversion FIFO. Thirty-two consecutive
conversions can be completed and stored in the FIFO without any microprocessor intervention. The
microprocessor can, at any time, interrogate the FIFO and retrieve its contents. It can also wait for the LM12L458
to issue an interrupt when the FIFO is full or after any number (≤32) of conversions have been stored.
Conversion sequencing, internal timer interval, multiplexer configuration, and many other operations are
programmed and set in the Instruction RAM.
A diagnostic mode is available that allows verification of the LM12L458's operation. This mode internally
connects the voltages present at the V
REF+
, V
REF−
, and GND pins to the internal V
IN+
and V
IN−
S/H inputs. This
mode is activated by setting the Diagnostic bit (Bit 11) in the Configuration register to a “1”. More information
concerning this mode of operation can be found in CONFIGURATION REGISTER.
Internal User-Programmable Registers
INSTRUCTION RAM
The instruction RAM holds up to eight sequentially executable instructions. Each 48-bit long instruction is divided
into three 16-bit sections. READ and WRITE operations can be issued to each 16-bit section using the
instruction's address and the 2-bit “RAM pointer” in the Configuration register. The eight instructions are located
at addresses 0000 through 0111 (A4–A1, BW = 0) when using a 16-bit wide data bus or at addresses 00000
through 01111 (A4–A0, BW = 1) when using an 8-bit wide data bus. They can be accessed and programmed in
random order.
Any Instruction RAM READ or WRITE can affect the sequencer's operation:
The Sequencer should be stopped by setting the RESET bit to a “1” or by resetting the START bit in the
Configuration Register and waiting for the current instruction to finish execution before any Instruction RAM
READ or WRITE is initiated. Bit 0 of the Configuration Register indicates the Sequencer Status. See
CONFIGURATION REGISTER for information on the Configuration Register.
A soft RESET should be issued by writing a “1” to the Configuration Register's RESET bit after any READ or
WRITE to the Instruction RAM.
The three sections in the Instruction RAM are selected by the Configuration Register's 2-bit “RAM Pointer”, bits
D8 and D9. The first 16-bit Instruction RAM section is selected with the RAM Pointer equal to “00”. This section
provides multiplexer channel selection, as well as resolution, acquisition time, etc. The second 16-bit section
holds “watchdog” limit #1, its sign, and an indicator that shows that an interrupt can be generated if the input
signal is greater or less than the programmed limit. The third 16-bit section holds “watchdog” limit #2, its sign,
and an indicator that shows that an interrupt can be generated if the input signal is greater or less than the
programmed limit.
Instruction RAM “00”
Bit 0 is the LOOP bit. It indicates the last instruction to be executed in any instruction sequence when it is set to
a “1”. The next instruction to be executed will be instruction 0.
Bit 1 is the PAUSE bit. This controls the Sequencer's operation. When the PAUSE bit is set (“1”), the Sequencer
will stop after reading the current instruction, but before executing it and the start bit, in the Configuration
register, is automatically reset to a “0”. Setting the PAUSE also causes an interrupt to be issued. The Sequencer
is restarted by placing a “1” in the Configuration register's Bit 0 (Start bit).
After the Instruction RAM has been programmed and the RESET bit is set to “1”, the Sequencer retrieves
Instruction 000, decodes it, and waits for a “1” to be placed in the Configuration's START bit. The START bit
value of “0” “overrides” the action of Instruction 000's PAUSE bit when the Sequencer is started. Once started,
the Sequencer executes Instruction 000 and retrieves, decodes, and executes each of the remaining instructions.
No PAUSE Interrupt (INT 5) is generated the first time the Sequencer executes Instruction 000 having a PAUSE
bit set to “1”. When the Sequencer encounters a LOOP bit or completes all eight instructions, Instruction 000 is
retrieved and decoded. A set PAUSE bit in Instruction 000 now halts the Sequencer before the instruction is
executed.
Bits 2–4 select which of the eight input channels (“000” to “111” for IN0–IN7) will be configured as non-inverting
inputs to the LM12L458's ADC. (See Table 4.)
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