Datasheet

LM12L458
www.ti.com SNAS085B –JULY 1999–REVISED MARCH 2013
or non-adjacent, can operate as a fully differential pair.
V
REF−
This is the negative reference input. The LM12L458 operates with 0V ≤ V
REF−
≤ V
REF+
. This pin should be
bypassed to ground with a parallel combination of 10 μF and 0.1 μF (ceramic) capacitors.
V
REF+
Positive reference input. The LM12L458 operate with 0V ≤ V
REF+
≤ V
A
+. This pin should be bypassed to
ground with a parallel combination of 10 μF and 0.1 μF (ceramic) capacitors.
N.C. This is a no connect pin.
FUNCTIONAL DESCRIPTION
The LM12L458 is a multi-functional Data Acquisition System that includes a fully differential 12-bit-plus-sign self-
calibrating analog-to-digital converter (ADC) with a two's-complement output format, an 8-channel analog
multiplexer, a first-in-first-out (FIFO) register that can store 32 conversion results, and an Instruction RAM that
can store as many as eight instructions to be sequentially executed. All of this circuitry operates on only a single
+3.3V power supply.
The LM12L458 has three modes of operation:
1. 12-bit + sign with correction
2. 8-bit + sign without correction
3. 8-bit + sign comparison mode (“watchdog” mode)
The fully differential 12-bit-plus-sign ADC uses a charge redistribution topology that includes calibration
capabilities. Charge re-distribution ADCs use a capacitor ladder in place of a resistor ladder to form an internal
DAC. The DAC is used by a successive approximation register to generate intermediate voltages between the
voltages applied to V
REF−
and V
REF+
. These intermediate voltages are compared against the sampled analog
input voltage as each bit is generated. The number of intermediate voltages and comparisons equals the ADC's
resolution. The correction of each bit's accuracy is accomplished by calibrating the capacitor ladder used in the
ADC.
Two different calibration modes are available; one compensates for offset voltage, or zero error, while the other
corrects both offset error and the ADC's linearity error.
When correcting offset only, the offset error is measured once and a correction coefficient is created. During the
full calibration, the offset error is measured eight times, averaged, and a correction coefficient is created. After
completion of either calibration mode, the offset correction coefficient is stored in an internal offset correction
register.
The LM12L458's overall linearity correction is achieved by correcting the internal DAC's capacitor mismatch.
Each capacitor is compared eight times against all remaining smaller value capacitors and any errors are
averaged. A correction coefficient is then created and stored in one of the thirteen internal linearity correction
registers. An internal state machine, using patterns stored in an internal 16 x 8-bit ROM, executes each
calibration algorithm.
Once calibrated, an internal arithmetic logic unit (ALU) uses the offset correction coefficient and the 13 linearity
correction coefficients to reduce the conversion's offset error and linearity error, in the background, during the 12-
bit + sign conversion. The 8-bit + sign conversion and comparison modes use only the offset coefficient. The 8-
bit + sign mode performs a conversion in less than half the time used by the 12-bit + sign conversion mode.
The LM12L458's “watchdog” mode is used to monitor a single-ended or differential signal's amplitude. Each
sampled signal has two limits. An interrupt can be generated if the input signal is above or below either of the
two limits. This allows interrupts to be generated when analog voltage inputs are “inside the window” or,
alternatively, “outside the window”. After a “watchdog” mode interrupt, the processor can then request a
conversion on the input signal and read the signal's magnitude.
The analog input multiplexer can be configured for any combination of single-ended or fully differential operation.
Each input is referenced to ground when a multiplexer channel operates in the single-ended mode. Fully
differential analog input channels are formed by pairing any two channels together.
The LM12L458's internal S/H is designed to operate at its minimum acquisition time (1.5 μs, 12 bits) when the
source impedance, R
S
, is ≤ 80Ω (f
CLK
≤ 6 MHz). When 80Ω < R
S
≤ 5.56 kΩ, the internal S/H's acquisition time
can be increased to a maximum of 6.5 μs (12 bits, f
CLK
= 6 MHz). See INSTRUCTION RAM (Instruction RAM
“00”) Bits 12–15 for more information.
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