Datasheet

LM12L458
www.ti.com SNAS085B –JULY 1999–REVISED MARCH 2013
Figure 29. Non-Multiplexed Data Bus (ALE = 1)
8: RD pulse width 16: RD low to data bus out of TRI-STATE
9: RD high to next RD or WR low 17: RD high to TRI-STATE
11: WR pulse width 18: RD low to data valid (access time)
13: WR high to next WR or RD low 19: Address invalid from RD or WR high (hold time)
14: Data valid to WR high set-up time 20: CS low or address valid to RD low
15: Data valid to WR high hold time 21: CS low or address valid to WR low
V
A
+ = V
D
+ = +3.3V, t
R
= t
F
= 3 ns, C
L
= 100 pF for the INT, DMARQ, D0–D15 outputs.
Figure 30. Interrupt and DMARQ
22: INT high from RD low 23: DMARQ low from RD low
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